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rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a ad9887 one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 www.analog.com fax: 781/326-8703 ? analog devices, inc., 2001 dual interface for flat panel displays features analog interface 140 msps maximum conversion rate 330 mhz analog bandwidth 0.5 v to 1.0 v analog input range 500 ps p-p pll clock jitter at 140 msps 3.3 v power supply full sync processing midscale clamp 4:2:2 output format mode digital (dvi 1.0 compatible) interface 112 mhz operation (1 pixel/clock mode) high skew tolerance of one full input clock sync detect for hot plugging applications rgb graphics processing lcd monitors and projectors plasma display panels scan converters micro displays digital tv general description the ad9887 offers designers the flexibility of a dual analog and digital interface for flat panel displays (fpds) on a single chip. both interfaces are optimized for excellent image quality supporting display resolutions up to sxga (1280 1024 at 75 hz). either the analog or the digital interface can be selected by the user. analog interface for ease of design and to minimize cost, the ad9887 is a fully integrated interface solution for fpds. the ad9887 includes an analog interface with a 140 mhz triple adc with internal 1.25 v reference, pll to generate a pixel clock from hsync, pro gram- mable gain, offset, and clamp control. the user provides only a 3.3 v power supply, analog input, and hsync. three-state cmos outputs may be powered from 2.5 v to 3.3 v. the ad9887s on-chip pll generates a pixel clock from hsync. pixel clock output frequencies range from 12 mhz to 140 mhz. pll clock jitter is 500 ps p-p typical at 140 msps. when a coast signal is presented, the pll maintains its output fre- quency in the absence of hsync. a sampling phase adjustment is provided. data, hsync and clock output phase relationships are maintained. the pll can be disabled and an external clock input provided as the pixel clock. the ad9887 also offers full sync pro- cessing for composite sync and sync-on-green applications. a clamp signal is generated internally or may be provided by the user through the clamp input pin. the analog interface is fully programmable via a 2-wire serial interface. functional block diagram serial register and power management scl sda a 1 a 0 2 datack hsout vsout sogout rx0+ rx0 rx1+ rx1 rx2+ rx2 rxc+ rxc r term dvi receiver 8 8 8 r outa r outb 8 8 8 g outa g outb 8 8 8 b outa b outb 2 datack de hsync vsync ad9887 digital interface r outa r outb g outa g outb b outa b outb hsout vsout sogout de datack 8 8 8 8 8 8 2 sync processing and clock generation hsync coast clamp ckinv ckext filt clamp r ain clamp g ain clamp b ain a/d 8 8 8 r outa r outb a/d 8 8 8 g outa g outb a/d 8 8 8 b outa b outb analog interface m u x e s vsync s cdt refin ref refout digital interface the ad9887 contains a digital video interface (dvi 1.0) compat- ible receiver. this receiver supp orts displays ranging from vga to sxga (25 mhz to 112 mhz). the receiver operates with true color (24-bit) panels in 1 or 2 pixel(s)/clock mode, and also features an intrapair skew tolerance up to one full clock cycle. fabricated in an advanced cmos process, the ad9887 is pro- vided in a 160-lead mqfp surface mount plastic package and is speci?ed over the 0 c to 70 c temperature range.
rev. 0 C2C ad9887?pecifications analog interface test ad9887ks-100 ad9887ks-140 parameter temp level min typ max min typ max unit resolution 8 8 bits dc accuracy differential nonlinearity 25 ci 0.5 +1.15/C1.0 0.5 +1.25/C1.0 lsb full vi +1.15/C1.0 +1.25/C1.0 lsb integral nonlinearity 25 ci 0.5 1.40 0.5 1.4 lsb full vi 1.75 2.5 lsb no missing codes full vi guaranteed guaranteed analog input input voltage range minimum full vi 0.5 0.5 v p-p maximum full vi 1.0 1.0 v p-p gain tempco 25 c v 135 150 ppm/ c input bias current 25 civ 1 1 a full iv 1 1 a input offset voltage full vi 7 50 7 50 mv input full-scale matching full vi 8.0 8.0 % fs offset adjustment range full vi 44 50 56 44 50 56 % fs reference output output voltage full vi 1.20 1.25 1.30 1.20 1.25 1.30 v temperature coef?cient full v 50 50 ppm/ c switching performance 1 maximum conversion rate full vi 100 140 msps minimum conversion rate full iv 10 10 msps clock to data skew, t skew full iv C0.5 +2.0 C0.5 +2.0 ns t buff full vi 4.7 4.7 s t stah full vi 4.0 4.0 s t dho full vi 0 0 s t dal full vi 4.7 4.7 s t dah full vi 4.0 4.0 s t dsu full vi 250 250 ns t stasu full vi 4.7 4.7 s t stosu full vi 4.0 4.0 s hsync input frequency full iv 15 110 15 110 khz maximum pll clock rate full vi 100 140 mhz minimum pll clock rate full iv 12 12 mhz pll jitter 25 c iv 400 700 2 400 700 3 ps p-p full iv 1000 2 1000 3 ps p-p sampling phase tempco full iv 15 15 ps/ c digital inputs input voltage, high (v ih ) full vi 2.6 2.6 v input voltage, low (v il ) full vi 0.8 0.8 v input current, high (v ih ) full iv C1.0 C1.0 a input current, low (v il ) full iv 1.0 1.0 a input capacitance 25 cv 3 3 pf digital outputs output voltage, high (v oh ) full vi 2.4 2.4 v output voltage, low (v ol ) full vi 0.4 0.4 v duty cycle datack, datack full iv 45 50 55 45 50 55 % output coding binary binary (v d = 3.3 v, v dd = 3.3 v, adc clock = maximum conversion rate, unless otherwise noted.)
rev. 0 C3C ad9887 test ad9887ks-100 ad9887ks-140 parameter temp level min typ max min typ max unit power supply v d supply voltage full iv 3.0 3.3 3.6 3.0 3.3 3.6 v v dd supply voltage full iv 2.2 3.3 3.6 2.2 3.3 3.6 v p vd supply voltage full iv 3.0 3.3 3.6 3.0 3.3 3.6 v i d supply current (v d )25 c v 140 155 ma i dd supply current (v dd ) 4 25 c v 34 48 ma ip vd supply current (p vd )25 c v 15 16 ma total supply current 4 full vi 170 258 215 258 ma power-down supply current full vi 18 25 18 25 ma dynamic performance analog bandwidth, full power 25 c v 330 330 mhz transient response 25 cv 2 2 ns overvoltage recovery time 25 c v 1.5 1.5 ns signal-to-noise ratio (snr) 5 25 c v 46 46 db (without harmonics) full v 45 45 db f in = 40.7 mhz crosstalk full v 60 60 dbc thermal characteristics ja junction-to-ambient 6 v30 30 c/w thermal resistance notes 1 drive strength = 11. 2 vco range = 01, charge pump current = 001, pll divider = 1693. 3 vco range = 10, charge pump current = 110, pll divider = 1600. 4 demux = 1, datack and datack load = 10 pf, data load = 5 pf. 5 using external pixel clock. 6 simulated typical performance with package mounted to a 4-layer board. speci?cations subject to change without notice.
rev. 0 C4C ad9887?pecifications digital interface test ad9887ks parameter conditions level min typ max unit resolution 8 bits dc digital i/o specifications high-level input voltage, (v ih ) vi 2.6 v low-level input voltage, (v il ) vi 0.8 v high-level output voltage, (v oh ) vi 2.4 v low-level output voltage, (v ol ) vi 0.4 v input clamp voltage, (v cinl )(i cl = C18 ma) iv gnd C 0.8 v input clamp voltage, (v cipl )(i cl = +18 ma) iv v dd + 0.8 v output clamp voltage, (v conl )(i cl = C18 ma) iv gnd C 0.8 v output clamp voltage, (v copl )(i cl = +18 ma) iv v dd + 0.8 v output leakage current, (i ol ) (high impedance) iv C10 +10 a dc specifications output high drive output drive = high iv 13 ma (i ohd ) (v out = v oh ) output drive = med iv 8 ma output drive = low iv 5 ma output drive = high iv C9 ma (i old ) (v out = v ol ) output drive = med iv C7 ma output drive = low iv C5 ma output drive = high iv 25 ma (v ohc ) (v out = v oh ) output drive = med iv 12 ma output drive = low iv 8 ma datack low drive output drive = high iv C25 ma (v olc ) (v out = v ol ) output drive = med iv C19 ma output drive = low iv C8 ma differential input voltage single-ended amplitude iv 75 800 mv power supply v d supply voltage iv 3.0 3.3 3.6 v v dd supply voltage minimum value for 2 pixels per clock mode iv 2.2 3.3 3.6 v p vd supply voltage iv 3.0 3.3 3.6 v v d supply current (typical pattern) 1 v 274 ma v dd supply current (typical pattern) 1, 4 v38 ma p vd supply current (typical pattern) 1 v21 ma total supply current (typical pattern) 1, 4 vi 362 ma v d supply current (worst-case pattern) 2 v 280 ma v dd supply current (worst-case pattern) 2, 4 v75 ma p vd supply current (worst-case pattern) 2 v21 ma total supply current (worst-case pattern) 2, 4 vi 400 ma power-down supply current (i pd )vi1325ma ac specifications intrapair (+ to C) differential input skew (t dps ) iv 360 ps channel-to-channel differential input skew (t ccs ) iv 1.0 clock period low-to-high transition time for data and output drive = high; c l = 10 pf iv 2.0 ns controls (d lht ) output drive = med; c l = 7 pf iv 3.0 ns output drive = low; c l = 5 pf iv 3.4 ns low-to-high transition time for datack (d lht ) output drive = high; c l = 10 pf iv 1.3 ns output drive = med; c l = 7 pf iv 1.9 ns output drive = low; c l = 5 pf iv 2.5 ns high-to-low transition time for data and output drive = high; c l = 10 pf iv 2.7 ns controls (d hlt ) output drive = med; c l = 7 pf iv 3.0 ns output drive = low; c l = 5 pf iv 3.3 ns (v d = 3.3 v, v dd = 3 v, clock = maximum)
rev. 0 C5C ad9887 test ad9887ks parameter conditions level min typ max unit ac specifications (continued) high-to-low transition time for datack (d hlt ) output drive = high; c l =10 pf iv 1.4 ns output drive = med; c l = 7 pf iv 1.7 ns output drive = low; c l = 5 pf iv 2.1 ns clock to data skew, t skew iv C0.5 +2.0 ns duty cycle, t dcycle iv 45 55 % of period high datack frequency (f cip ) (1 pixel/clock) vi 20 112 mhz datack frequency (f cip ) (2 pixels/clock) iv 10 56 mhz notes 1 the typical pattern contains a gray scale area, output drive = high. 2 the worst-case pattern contains a black and white checkerboard pattern, output drive = high. 3 the setup and hold times with respect to the datack rising edge are the same as the falling edge. 4 1 pixel/clock mode, datack and datack load = 10 pf, data load = 5 pf. caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the ad9887 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. warning! esd sensitive device absolute maximum ratings * v d . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6 v v dd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6 v analog inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . v d to 0.0 v vref in . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v d to 0.0 v digital inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 v to 0.0 v digital output current . . . . . . . . . . . . . . . . . . . . . . . . 20 ma operating temperature . . . . . . . . . . . . . . . . . C25 c to +85 c storage temperature . . . . . . . . . . . . . . . . . . C65 c to +150 c maximum junction temperature . . . . . . . . . . . . . . . . 150 c maximum case temperature . . . . . . . . . . . . . . . . . . . 150 c * stresses above those listed under absolute maximum ratings may cause perma- nent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions outside of those indicated in the operation sections of this speci?cation is not implied. exposure to absolute maximum ratings for extended periods may affect device reliability. explanation of test levels test level explanation i 100% production tested. ii 100% production tested at 25 c and sample tested at speci?ed temperatures. iii sample tested only. iv parameter is guaranteed by design and charac- terization testing. v parameter is a typical value only. vi 100% production tested at 25 c; guaranteed by design and characterization testing. ordering guide temperature package package model range description option ad9887ks-140 0 c to 70 c plastic quad flatpack s-160 ad9887ks-100 0 c to 70 c plastic quad flatpack s-160 ad9887/pcb 25 c evaluation board
rev. 0 C6C ad9887 pin configuration red b<0> red b<1> red b<2> red b<3> red b<4> red b<5> red b<6> red b<7> gnd v dd red a<0> red a<1> red a<2> red a<3> red a<4> red a<5> red a<6> red a<7> gnd v dd sogout hsout vsout de s cdt datack datack gnd v dd gnd gnd scan in gnd v d ref out ref in v d v d gnd gnd 160 159 158 157 156 155 154 153 152 151 150 149 147 146 145 144 143 142 141 140 139 138 148 137 136 135 133 132 131 130 129 128 134 127 126 125 123 122 121 124 gnd gnd v dd gnd scan out ctl0 ctl1 ctl2 ctl3 scan clk v d gnd r term v d v d rx2+ rx2 gnd rx1+ rx1 gnd rx0+ rx0 gnd rxc+ rxc v d v d gnd v d nc nc nc gnd pv d gnd pv d filt pv d gnd 53 54 55 56 57 58 59 60 61 62 41 42 43 44 45 46 47 48 49 50 51 52 63 64 65 66 68 69 70 71 72 67 73 74 75 76 78 79 80 77 5 4 3 2 7 6 9 8 1 14 13 12 11 16 15 17 10 19 18 23 22 21 20 25 24 27 26 29 28 32 31 30 34 33 36 35 40 39 38 37 v dd gnd green a<7> green a<6> green a<5> green a<4> green a<3> green a<2> green a<1> green a<0> v dd gnd green b<7> green b<6> green b<5> green b<4> green b<3> green b<2> green b<1> green b<0> v dd gnd blue a<7> blue a<6> blue a<5> blue a<4> blue a<3> blue a<2> blue a<1> blue a<0> v dd gnd blue b<7> blue b<6> blue b<5> blue b<4> blue b<3> blue b<2> blue b<1> blue b<0> r midsc v r ain r clamp v v d gnd v d v d gnd gnd g midsc v g ain g clamp v sogin v d gnd v d v d gnd gnd b midsc v b ain b clamp v v d gnd v d gnd ckinv clamp sda scl a0 a1 pv d pv d gnd gnd coast ckext hsync vsync 104 119 120 114 115 116 117 112 113 111 118 109 110 105 106 107 108 102 103 100 101 98 99 95 96 97 93 94 91 92 90 87 88 89 86 84 85 82 83 81 pin 1 identifier top view (not to scale) ad9887 nc = no connect
rev. 0 ad9887 C7C table i. complete pinout list p in pin pin type name function value number interface analog video r ain analog input for converter r 0.0 v to 1.0 v 119 analog inputs g ain analog input for converter g 0.0 v to 1.0 v 110 analog b ain analog input for converter b 0.0 v to 1.0 v 100 analog external hsync horizontal sync input 3.3 v cmos 82 analog sync/clock vsync vertical sync input 3.3 v cmos 81 analog inputs sogin input for sync-on-green 0.0 v to 1.0 v 108 analog clamp clamp input (external clamp signal) 3.3 v cmos 93 analog coast pll coast signal input 3.3 v cmos 84 analog ckext external pixel cl ock input (to bypass the pll) to v dd or ground 3.3 v cmos 83 analog ckinv adc sampling clock invert 3.3 v cmos 94 analog sync outputs hsout hsync output clock (phase-aligned with datack) 3.3 v cmos 139 both vsout vsync output clock (phase-aligned with datack) 3.3 v cmos 138 both sogout sync on green slicer output 3.3 v cmos 140 analog voltage refout internal reference output (bypass with 0.1 f to ground) 1.25 v 126 analog reference refin reference input (1.25 v 10%) 1.25 v 10% 125 analog clamp voltages r midsc v red channel midscale clamp voltage output 120 analog r clamp v red channel midscale clamp voltage input 0.0 v to 0.75 v 118 analog g midsc v green channel midscale clamp voltage output 111 analog g clamp v green channel midscale clamp voltage input 0.0 v to 0.75 v 109 analog b midsc v blue channel midscale clamp voltage output 101 analog b clamp v blue channel midscale clamp voltage input 0.0 v to 0.75 v 99 analog pll filter filt connection for external filter components for internal pll 78 analog power supply v d analog power supply 3.3 v 10% both v dd output power supply 3.3 v 10% both pv d pll power supply 3.3 v 10% both gnd ground 0 v both serial port sda serial port data i/o 3.3 v cmos 92 both (2-wire scl serial port data clock (100 khz max) 3.3 v cmos 91 both serial interface) a0 serial port address input 1 3.3 v cmos 90 both a1 serial port address input 2 3.3 v cmos 89 both data outputs red b[7:0] port b/odd outputs of converter red, bit 7 is the msb 3.3 v cmos 153C160 both green b[7:0] port b/ odd outputs of converter green, bit 7 is the msb 3.3 v cmos 13C20 both blue b[7:0] port b/odd outputs of converter blue, bit 7 is the msb 3.3 v cmos 33C40 both red a[7:0] port a/even outputs of converter red, bit 7 is the msb 3.3 v cmos 143C150 both green a[7:0] port a/even outputs of converter green, bit 7 is the msb 3.3 v cmos 3C10 both blue a[7:0] port a/even outputs of converter blue, bit 7 is the msb 3.3 v cmos 23C30 both data clock datack data output clock for the analog and digital interface 3.3 v cmos 134 both outputs datack data output clock complement for the analog interface only 3.3 v cmos 135 both sync detect s cdt sync detect output 3.3 v cmos 136 both scan function scan in input for scan function 3.3 v cmos 129 both scan out output for scan function 3.3 v cmos 45 both scan clk clock for scan function 3.3 v cmos 50 both no connect nc these pins should be left unconnected 71C73 both digital video r x0 + digital input channel 0 true 62 digital data inputs r x0 C digital input channel 0 complement 63 digital r x1 + digital input channel 1 true 59 digital r x1 C digital input channel 1 complement 60 digital r x2 + digital input channel 2 true 56 digital r x2 C digital input channel 2 complement 57 digital digital video r xc + digital data clock true 65 digital clock inputs r xc C digital data clock complement 66 digital data enable de data enable 3.3 v cmos 137 digital control bits ctl[0:3] decoded control bits 3.3 v cmos 46C49 digital r term r term sets internal termination resistance 53 digital
rev. 0 C8C ad9887 descriptions of pins shared between analog and digital interfaces hsout horizontal sync output a reconstructed and phase-aligned version of the video hsync. the polarity of this output can be controlled via a serial bus bit. in analog interface mode the placement and duration are variable. in digital interface mode the placement and duration are set by the graphics transmitter. vsout vertical sync output the separated vsync from a composite signal or a direct pass through of the vsync input. the polarity of this output can be con- trolled via a serial bus bit. the placement and duration in all modes is set by the graphics transmitter. serial port (2-wire) sda serial port data i/o scl serial port data clock a0 serial port address input 1 a1 serial port address input 2 for a full description of the 2-wire serial regis- ter and how it works, refer to the control register section. data outputs red a data output, red channel, port a/even red b data output, red channel, port b/odd green a data output, green channel, port a/even green b data output, green channel, port b/odd blue a data output, blue channel, port a/even blue b data output, blue channel, port b/odd the main data outputs. bit 7 is the msb. these outputs are shared between the two interfaces and behave according to which interface is active. refer to the sections on the two interfaces for more information on how these outputs behave. data clock outputs datack data output clock datack data output clock complement just like the data outputs, the data clock out- puts are shared between the two interfaces. they also behave differently depending on which interface is active. refer to the sections on the two interfaces to determine how these pins behave. various s cdt chip active/inactive detect output the logic for the s cdt pin is [analog interface hsync detection] or [digital interface de detection]. so, the s cdt pin will sw itch to logic low under two conditions, when nei- ther interface is active or when the chip is in full chip power-down mode. the data outputs are automatically three-stated when s cdt is low. this pin can be read by a controller in order to determine periods of inactivity. scan function scan in data input for scan function data can be loaded serially into the 48-bit scan register through this pin, clocking it in with the scan clk pin. it then comes out of the 48 data outputs in parallel. this function is useful for loading known data into a graph- ics controller chip for testing purposes. scan out data output for scan function the data in the 48-bit scan register can be read through this pin. data is read on a fifo basis and is clocked via the scan clk pin. scan clk data clock for scan function this pin clocks the data through the scan register. it controls both data input and data output.
rev. 0 ad9887 C9C table ii. analog interface pin list pin type pin name function value pin no. analog video inputs r ain analog input for converter r 0.0 v to 1.0 v 119 g ain analog input for converter g 0.0 v to 1.0 v 110 b ain analog input for converter b 0.0 v to 1.0 v 100 external hsync horizontal sync input 3.3 v cmos 82 vsync vertical sync input 3.3 v cmos 81 sync/clock sogin sync-on-green input 0.0 v to 1.0 v 108 inputs clamp clamp input (external clamp signal) 3.3 v cmos 93 coast pll coast signal input 3.3 v cmos 84 ckext external pixel clock input (to bypass internal pll) 3.3 v cmos 83 or 10 k ? to v dd ckinv adc sampling clock invert 3.3 v cmos 94 sync outputs hsout hsync output (phase-aligned with datack and datack ) 3.3 v cmos 139 vsout vsync output (asynchronous) 3.3 v cmos 138 sogout sync-on-green slicer output or raw hsync output 3.3 v cmos 140 voltage reference refout internal reference output (bypass with 0.1 f to ground) 1.25 v 126 refin reference input (1.25 v 10%) 1.25 v 10% 125 clamp voltages r midsc v voltage output equal to the red converter midscale voltage. 0.5 v 50% 120 r clamp v during midscale clamping, the red input is clamped to this pin. 0.0 v to 0.75 v 118 g midsc v voltage output equal to the green converter midscale voltage. 0.5 v 50% 111 g clamp v during midscale clamping, the green input is clamped to this pin. 0.0 v to 0.75 v 109 b midsc v voltage output equal to the blue converter midscale voltage. 0.5 v 50% 101 b clamp v during midscale clamping, the blue input is clamped to this pin. 0.0 v to 0.75 v 99 pll filter filt connection for external filter components for internal pll 78 power supply v d main power supply 3.3 v 5% pv d pll power supply (nominally 3.3 v) 3.3 v 5% v dd output power supply 3.3 v or 2.5 v 5% gnd ground 0 v pin function details (analog interface) inputs r ain analog input for red channel g ain analog input for green channel b ain analog input for blue channel high-impedance inputs that accept the red, green, and blue channel graphics sig nals, respectively. for rgb, the three channels are identical and can be used for any colors, but colors are assigned for convenient reference. for proper 4:2:2 formatting in a yuv appli- cation, the y channel must be connected to the g ain input, u must be connected to the b ain input, and v must be connected to the r ain input. they accommodate input signals ranging from 0.5 v to 1.0 v full scale. signals should be ac-coupled to these pins to support clamp operation. hsync horizontal sync input this input receives a logic signal that estab- lishes the horizontal timing reference and provides the frequency reference for pixel clock generation. the logic sense of this pin is controlled by serial register 0fh bit 7 ( hsync polarity). only the leading edge of hsync is active, the t railing edge is ignored. when hsync polarity = 0, the falling edge of hsync is used. when hsync polarity = 1, the rising edge is active. the input includes a schmitt trigger for noise immunity, with a nominal input threshold of 1.5 v. electrostatic discharge (esd) protection diodes will conduct heavily if this pin is driven more than 0.5 v above the maximum toler- ance voltage (3.3 v), or more than 0.5 v below ground. vsync vertical sync input this is the input for vertical sync. sogin sync-on-green input this input is provided to assist with processing signals with embedded sync, typically on the green channel. the pin is connected to a high-speed comparator with an internally generated threshold, which is set to 0.15 v above the negative peak of the input signal. when connected to an ac-coupled graphics signal with embedded sync, it will produce a noninverting digital output on sogout. when not used, this input should be left unconnected. for more details on this func- tion and how it should be con?gured, refer to the sync-on-green section.
rev. 0 C10C ad9887 clamp external clamp input (optional) this logic input may be used to de?ne the time during which the input signal is clamped to the reference dc level, (ground for rgb or midscale for yuv). it should be exercised when the reference dc level is known to be present on the analog input channels, typically during the back porch of the graphics signal. the clamp pin is enabled by setting control bit extclmp to 1, (the default power-up is 0). when disabled, this pin is ignored and the clamp timing is determined internally by counting a delay and duration from the trailing edge of the hsync input. the logic sense of this pin is controlled by clampol. when not used, this pin must be grounded and extclmp programmed to 0. coast clock generator coast input (optional) this input may be used to cause the pixel clock generator to stop synchronizing with hsync and continue producing a clock at its current frequency and phase. this is useful when processing signals from sources that fail to produce horizontal sync pulses when in the vertical interval. the coast signal is generally not required for pc-generated signals. appli- cations requiring coast can do so through the internal coast found in the sync processing engine. the logic sense of this pin is controlled by coast polarity. when not used, this pin may be grounded and coast polarity programmed to 1, or tied high and coast polarity programmed to 0. coast polarity defaults to 1 at power-up. ckext external clock input (optional) this pin may be used to provide an external clock to the ad9887, in place of the clock internally generated from hsync. it is enabled by programming extclk to 1. when an external clock is used, all other internal functions operate normally. when unused, this pin should be tied to v dd or to ground, and extclk programmed to 0. the clock phase adjustment still operates when an external clock source is used. ckinv sampling clock inversion (optional) this pin may be used to invert the pixel sampling clock, which has the effect of shifting the sampling phase 180 . this is in support of a lternate pixel sampling mode, wherein h igher-frequency input signals (up to 280 mpps) may be captured by ?rst sam- pling the odd pixels, then capturing the even pixels on the subsequent frame. this pin should be exercised only during blanking intervals (typically vertical blanking) as it may produce several samples of corrupted data during the phase shift. ckinv should be grounded when not used. outputs d r a 7-0 data output, red channel, port a d r b 7-0 data output, red channel, port b d g a 7-0 data output, green channel, port a d g b 7-0 data output, green channel, port b d b a 7-0 data output, blue channel, port a d b b 7-0 data output, blue channel, port b these are the main data outputs. bit 7 is the msb. each channel has two ports. when the part is operated in single-channel mode (demux = 0), all data are presented to port a, and port b is placed in a high-impedance state. programming demux to 1 established dual- channel mode, wherein alternate pixels are presented to port a and port b of each chan- nel. these will appear simultaneously, two pixels presented at the time of every second input pixel, when par is set to 1 (parallel mode). when par = 0, pixel data appear alternately on the two ports, one new sample with each incoming pixel (interleaved mode). in dual channel mode, the ?rst pixel after hsync is routed to port a. the second pixel goes to port b, the third to a, etc. the delay from pixel sampling time to output is ?xed. when the sampling time is changed by adjusting the phase register, the output timing is shifted as well. the datack, datack , and hsout outputs are also moved, so the timing relatio nship among the signals is maintained. datack data output clock datack data output clock complement differential data clock output signals to be used to strobe the output data and hsout into external logic. they are produced by the internal clock gen- erator and are synchronous with the internal pixel sampling clock. when the ad9887 is operated in single-chan- nel mode, the output frequency is equal to the pixel sampling frequency. when operating in dual channel mode, the clock frequency is one- half the pixel frequency. when the sampling time is changed by adjusting the phase register, the output timing is shifted as well. the data, datack, datack, and hsout outputs are all moved, so the timing relationship among the signals is maintained.
rev. 0 ad9887 C11C either or both signals may be used, depend- ing on the timing mode and interface design employed. hsout horizontal sync output a reconstructed and phase-aligned version of the hsync input. both the polarity and dura- tion of this output can be programmed via serial bus registers. by maintaining alignment with datack, datack , and data, data timing with respect to horizontal sync can always be determined. sogout sync-on-green slicer output this pin can be programmed to output either the output from the sync-on-green slicer comparator or an unprocessed but delayed version of the hsync input. see the sync block diagram to view how this pin is connected. (note: the output from this pin is the sliced sog, without additional processing from the ad9887.) analog interface refout internal reference output output from the internal 1.25 v bandgap refer- ence. this output is intended to drive relatively light loads. it can drive the ad9887 reference input directly, but should be externally buff- ered if it is used to drive other loads as well. the absolute accuracy of this output is 4%, and the temperature coef?cient is 50 ppm, which is adequate for most ad9887 appli- cations. if higher accuracy is required, an external reference may be employed instead. if an external reference is used, connect this pin to ground through a 0.1 f capacitor. refin reference input the reference input accepts the master refer- ence voltage for all ad9887 internal circuitry (1.25 v 10%). it may be driven directly by the refout pin. its high impedance pre- sents a very light load to the reference source. this pin should always be bypassed to ground with a 0.1 f capacitor. filt external filter connection for proper operation, the pixel clock genera- tor pll requires an external ?lter. connect the ?lter shown figure 7 to this pin. for optimal performance, minimize noise and parasitics on this node. power supply v d main power supply these pins supply power to the main elements of the circuit. it should be ?ltered to be as quiet as possible. v dd digital output power supply these supply pins are identi?ed separately from the v d pins so special care can be taken to minimize output noise transferred into the sensitive analog circuitry. if the ad9887 is interfacing with lower- voltage logic, v dd may be connected to a lower supply voltage (as low as 2.2 v) for compatibility. pv d clock generator power supply the most sensitive portion of the ad9887 is the clock generation circuitry. these pins provide power to the clock pll and help the user design for optimal performance. the designer should provide noise-free power to these pins. gnd ground the ground return for all circuitry on chip. it is recommended that the application circuit board have a single, solid ground plane. theory of operation (interface detection) active interface detection and selection the ad9887 includes circuitry to detect whether or not an interface is active. for detecting the analog interface, the circuitry monitors the presence of hsync, vsync, and sync-on-green. the result of the detection circuitry can be read from the 2-wire serial inter- face bus at address 11h bits 7, 6, and 5 respectively. if one of these sync signals disappears, the maximum time it takes for the circuitry to detect it is 100 ms. there are two stages for detecting the digital interface. the ?rst stage searches for the presence of the digital interface clock. the circuitry for detecting the digital interface clock is active even when the digital interface is powered down. the result of this detection stage can be read from the 2-wire serial interface bus at address 11h bit 4. if the clock disappears, the maximum time it takes for the circuitry to detect it is 100 ms. the second stage attempts to detect de on the digital interface. detection is accomplished when 32 des have been counted. de can only be detected when the digital interface is powered up, so it is not always active. the de detection circuitry is one of the logic inputs used to set the syncdt output pin (pin 136). the logic for the syncdt pin is [de detect] or [hsync detect]. there is an override for the automatic interface selection. it is the aio bit (active interface override). when the aio bit is set to logic 0, the automatic circuitry will be used. when the aio bit is set to logic 1, the ais bit will be used to determine the active interface rather than the automatic circuitry.
rev. 0 C12C ad9887 table iii. interface selection controls analog digital active aio interface detect interface detect ais interface description 1 x x 0 analog force the analog interface active. 1 digital force the digital interface active. 0 0 0 x none neither interface was detected. both interfaces are powered down and the syncdt pin gets set to logic 0. 0 1 x digital the digital interface was detected. power down the analog interface. 1 0 x analog the analog interface was detected. power down the digital interface. 1 0 x analog both interfaces were detected. the analog interface has priority. 1 digital both interfaces were detected. the digital interface has priority. table iv. power-down mode descriptions inputs analog digital active active power- interface interface interface interface mode down 1 detect 2 detect 3 override select powered on or comments soft power-down (seek mode) 1 0 0 0 x serial bus, digital interface clock detect, analog interface activity detect, sog, bandgap reference digital interface on 1 0 1 0 x serial bus, digital interface, analog in terface activity detect, sog, outputs, bandgap reference analog interface on 1 1 0 0 x serial bus, analog interface, digital inter face clock detect, sog, outputs, bandgap reference serial bus arbitrated interface 1 1 1 0 0 same as analog interface on mode serial bus arbitrated interface 1 1 1 0 1 same as digital interface on mode override to analog interface 1 x x 1 0 same as analog interface on mode override to digital interface 1 x x 1 1 same as digital interface on mode absolute power-down 0 x x x x serial bus notes 1 power-down is controlled via bit 0 in serial bus register 12h. 2 analog interface detect is determined by or-ing bits 7, 6, and 5 in serial bus register 11h. 3 digital interface detect is determined by bit 4 in serial bus register 11h. power management the ad9887 is a dual interface device with shared outputs. only one interface can be used at a time. for this reason, the chip automatically powers down the unused interface. when the analog interface is being used, most of the digital interface circuitry is powered down and vice-versa. this helps to minimize the ad9887 total power dissipation. in addition, if neither inter- face has activity on it, the chip powers down both interfaces. the ad9887 uses the activity detect circuits, the active inter- face bits in the serial registers, the active interface override bits, and the power-down bit to determine the correct power state. in a given power mode not all circuitry in the inactive interface is powered down completely. when the digital interface is active, the bandgap reference and hsync detect circuitry is not powered down. w hen the analog interface is active, the digital interface clock detect circuit is not powered down. table iv summarizes how the ad9887 determines which power mode to be in and what circuitry is powered on/off in each of these modes. the power-down command has priority, followed by the active interface override, and then the automatic circuitry.
rev. 0 ad9887 C13C theory of operation and design guide (analog interface) general description the ad9887 is a fully integrated solution for capturing analog rgb signals and digitizing them for display on flat panel monitors or projectors. the device is ideal for implementing a computer inter face in hdtv monitors or as the front end to high- performance video scan converters. implemented in a high-performance cmos process, the inter- face can capture signals with pixel rates of up to 140 mhz and, with an alternate pixel sampling mode, up to 280 mhz. the ad9887 includes all necessary input buffering, signal dc restoration (clamping), offset and gain (brightness and contrast) adjustment, pixel clock generation, sampling phase control, and output data formatting. all controls are programmable via a 2-wire serial interface. full integration of these sensitive analog functions makes system design straightforward and less sensi- tive to the physical and electrical environment. with a typical power dissipation of less than 725 mw and an operating temperature range of 0 c to 70 c, the device re quires no special environmental considerations. input signal handling the ad9887 has three high-impedance analog input pins for the red, green, and blue channels. they will accommodate signals ranging from 0.5 v to 1.0 v p-p. signals are typically brought onto the interface board via a dvi-i connector, a 15-lead d connector, or bnc connectors. the ad9887 should be located as close as practical to the input connector. signals should be routed via matched-impedance traces (normally 75 ? ) to the ic input pins. at that point the signal should be resistively terminated (75 ? to the signal ground return) and capacitively coupled to the ad9887 inputs through 47 nf capacitors. these capacitors form part of the dc restoration circuit. in an ideal world of perfectly matched impedances, the best per- formance can be obtained with the widest possible signal bandwidth. the wide bandwidth inputs of the ad9887 (330 mhz) can track the input signal continuously as it moves from one pixel level to the next, and digitize the pixel during a long, flat pixel time. in many systems, however, there are mismatches, reflec- tions, and noise, which can result in excessive ringing and distortion of the input waveform. this makes it more dif?cult to establish a sampling phase that provides good image quality. it has been shown that a small inductor in series with the input is effective in rolling off the input bandwidth slightly, and pro- viding a high quality signal over a wider range of conditions. using a fair-rite #2508051217z0 high-speed signal chip bead inductor in the circuit of figure 1 gives good results in most applications. rgb input r ain g ain b ain 47nf 75 figure 1. analog input interface circuit hsync, vsync inputs the ad9887 receives a horizontal sync signal and uses it to generate the pixel clock and clamp timing. it is possible to operate the ad9887 without applying hsync (using an external clock, external clamp) but a number of features of the chip will be unavailable, so it is recommended that hsync be provided. this can be either a sync signal directly from the graphics source, or a preprocessed ttl or cmos level signal. the hsync input includes a schmitt trigger buffer and is capable of handling signals with long rise times, with superior noise immunity. in typical pc-based graphic systems, the sync signals are simply ttl-level drivers feeding unshielded wires in the monitor cable. as such, no termination is required or desired. when the vsync input is selected as the source for v sync , it is used for coast generation and is passed through to the vsout pin. serial control port the serial control port is designed for 3.3 v l ogic. if there are 5 v drivers on the bus, these pins should be protected with 150 ? series resistors placed between the pull-up resistors and the input pins. output signal handling the digital outputs are designed and speci?ed to operate from a 3.3 v power supply (v dd ). they can also work with a v dd as low as 2.5 v for compatibility with other 2.5 v logic. clamping rgb clamping to digitize the incoming signal properly, the dc offset of the input must be adjusted to ?t the range of the on-board a/d converters. most graphics systems produce rgb signals with black at ground and white at approximately 0.75 v. however, if sync signals are embedded in the graphics, the sync tip is often at ground and black is at 300 mv. the white level will then be approximately 1.0 v. some common rgb line ampli?er boxes use emitter-follower buffers to split signals and increase drive capability. this introduces a 700 mv dc offset to the signal, which is removed by clamping for proper capture by the ad9887. the key to clamping is to identify a portion (time) of the signal when the graphic system is known to be producing black. originating from crt displays, the electron beam is blanked by sending a black level during horizontal retrace to prevent disturbing the image. most graphics systems maintain this format of sending a black level between active video lines. an offset is then introduced which results in the a/d converters producing a black output (code 00h) when the known black input is present. the offset then remains in place when other signal levels are processed, and the entire signal is shifted to eliminate offset errors. in systems with embedded sync, a blacker-than-black signal (hsync) is produced briefly to signal the crt that it is time to begin a retrace. for obvious reasons, it is important to avoid
rev. 0 C14C ad9887 clamping on the tip of hsync. fortunately, there is virtually always a period following hsync called the back porch where a good black reference is provided. this is the time when clamp- ing should be done. the clamp timing can be established by exercising the clamp pin at the appropriate time (with extclmp = 1). the polarity of this signal is set by the clamp polarity bit. an easier method of clamp timing employs the ad9887 internal clamp timing generator. the clamp placement register is pro- grammed with the number of pixel clocks that should pass after the trailing edge of hsync before clamping starts. a second register (clamp duration) sets the duration of the clamp. these are both 8-bit values, providing considerable flexibility in clamp generation. the clamp timing is referenced to the trailing edge of hsync, the back porch (black reference) al ways follows hsync. a good starting point for establishing clamping is to set the clamp placement to 08h (providing eight pixel periods for the graphics signal to stabilize after sync) and set the clamp duration to 14h (giving the clamp 20 pixel periods to reestablish the black reference). the value of the external input coupling capacitor affects the per- formance of the clamp. if the value is too small, there can be an amplitude change during a horizontal line time (between clamping intervals). if the capacitor is too large, it will take excessively long for the clamp to recover from a large change in incoming signal offset. the recommended value (47 nf) results in recovery from a step error of 100 mv to within 1/2 lsb in 10 lines using a clamp duration of 20 pixel periods on a 60 hz sxga signal. yuv clamping yuv signals are slightly different from rgb signals in that the dc reference level (black level in rgb signals) will be at the midpoint of the u and v video signal. for these signals it can be necessary to clamp to the midscale range of the a/d con- verter range (80h) rather than bottom of the a/d converter range (00h). clamping to midscale rather than ground can be accomplished by setting the clamp select bits in the serial bus register. each of the three converters has its own selection bit so that they can be clamped to either midscale or ground independently. these bits are located in register 0fh and are bits 0C2. the midscale reference voltage that each a/d converter clamps to is provided independently on the r midsc v, g midsc v, and b midsc v pins. each converter must have its own midscale refer- ence because both offset adjustment and gain adjustment for each converter will affect the dc level of midscale. during clamping, the y and v converters are clamped to their respective midscale reference input. these inputs are pins b clamp v, and r clamp v for the u and v converters respectively. the typical connections for both rgb and yuv clamping are shown below in figure 2. note: if midscale clamping is not required, all of the midscale voltage outputs should still be con- nected to ground through a 0.1 f capacitor. r midsc v r clamp v g midsc v g clamp v b midsc v b clamp v 0.1 f 0.1 f 0.1 f figure 2. typical clamp con?guration for rbg/yuv applications gain and offset control the ad9887 can accommodate input signals with inputs rang- ing from 0.5 v to 1.0 v full scale. the full-scale range is set in three 8-bit registers (red gain, green gain, and blue gain). a code of 0 establishes a minimum input range of 0.5 v; 255 corresponds with the maximum range of 1.0 v. note that increasing the gain setting results in an image with less contrast. the offset control shifts the entire input range, resulting in a change in image brightness. three 7-bit registers (red offset, green offset, blue offset) provide independent settings for each channel. the offset controls provide a 63 lsb adjustment range. this range is connected with the full-scale range, so if the input range is doubled (from 0.5 v to 1.0 v) then the offset step size is also doubled (from 2 mv per step to 4 mv per step). figure 3 illustrates the interaction of gain and offset controls. the magnitude of an lsb in offset adjustment is proportional to the full-scale range, so changing the full-scale range also changes the offset. the change is minimal if the offset setting is near midscale. when changing the offset, the full-scale range is not affected, but the full-scale level is shifted by the same amount as the zero-scale level. gain 1.0 0.0 00h ffh input range v 0.5 offset = 00h offset = 3fh offset = 7fh offset = 00h offset = 7fh offset = 3fh figure 3. gain and offset control
rev. 0 ad9887 C15C sync-on-green the sync-on-green input operates in two steps. first, it sets a baseline clamp level from the incoming video signal with a negative peak detector. second, it sets the sync trigger level (nominally 150 mv above the negative peak). the exact trigger level is variable and can be programmed via register 11h. the sync-on-green input must be ac-coupled to the green analog input through its own capacitor as shown in figure 4. the value of the capacitor must be 1 nf 20%. if sync-on-green is not used, this connection is not required and sogin should be left unconnected. (note: the sync-on-green signal is always nega- tive polarity.) please refer to the sync processing section for more information. g ain sogin 47nf 1nf r ain 47nf b ain 47nf figure 4. typical clamp con?guration for rgb/yuv applications clock generation a phase locked loop (pll) is employed to generate the pixel clock. the hsync input provides a reference frequency for the pll. a voltage controlled oscillator (vco) generates a much higher pixel clock frequency. this pixel clock is divided by the pll divide value (registers 01h and 02h) and phase compared with the hsync input. any error is used to shift the vco fre- quency and maintain lock between the two signals. the stability of this clock is a very important element in provid- ing the clearest and most stable image. during each pixel time, there is a period when the signal is slewing from the old pixel amplitude and settling at its new value. then there is a time when the input voltage is stable, before the signal must slew to a new value (see figure 5). the ratio of the slewing time to the stable time is a function of the bandwidth of the graphics dac and the bandwidth of the transmission system (cable and t ermi- nation). it is also a function of the overall pixel rate. clearly, if the dynamic characteristics of the system remain ?xed, the slewing and settling times are likewise ?xed. this time must be sub- tracted from the total pixel period, leaving the stable period. at higher pixel frequencies, the total cycle time is shorter, and the stable pixel time becomes shorter as well. pixel clock mhz 14 12 0 0 jitter (p-p) % 10 8 6 4 2 135.0 25.2 31.5 36.0 40.0 50.0 56.3 65.0 75.0 78.8 85.5 94.5 108.0 figure 6. pixel clock jitter vs. frequency pixel clock invalid sample times figure 5. pixel sampling times any jitter in the clock reduces the precision with which the sampling time can be determined, and must also be subtracted from the stable pixel time. considerable care has been taken in the design of the ad9887s clock generation circuit to minimize jitter. as indicated in fig- ure 6, the clock jitter of the ad9887 is less than 6% of the total pixel time in all operating modes, making the reduction in the valid sampling time due to jitter negligible. the pll characteristics are determined by the loop ?lter design, by the pll charge pump current and by the vco range setting. the loop ?lter design is illustrated in figure 7. recom- mended settings of vco range and charge pump current for vesa standard display modes are listed in table vii. c p 0.0039 f c z 0.039 f r z 3.3k filt pv d figure 7. pll loop filter detail four programmable registers are provided to optimize the per- formance of the pll. these registers are: 1. the 12-bit divisor register. the input hsync frequencies range from 15 khz to 110 khz. the pll multiplies the frequency of the hsync signal, producing pixel clock fre- quencies in the range of 12 mhz to 140 mhz. the divisor register controls the exact multiplication factor. this register may be set to any value between 221 and 4095. (the divide ratio that is actually used is the programmed divide ratio plus one.) 2. the 2-bit vco range register. to lower the sensitivity of the output frequency to noise on the control signal, the vco operating frequency range is divided into four overlapping regions. the vco range register sets this operating range. because there are only four possible regions, only the two least-signi?cant bits of the vco range register are used. the frequency ranges for the lowest and highest regions are shown in table v.
rev. 0 C16C ad9887 table v. vco frequency ranges pixel clock k vco gain pv1 pv0 range (mhz) (mhz/v) 0 0 12C35 150 0 1 35C70 150 1 0 70C110 150 1 1 110C140 180 table vi. charge pump current/control bits ip2 ip1 ip0 current ( a) 00050 0 0 1 100 0 1 0 150 0 1 1 250 1 0 0 350 1 0 1 500 1 1 0 750 1 1 1 1500 3. the 3-bit charge pump current register. this register allows the current that drives the low pass loop ?lter to be varied. the possible current values are listed in table vi. provides 32 phase-shift steps of 11.25 each. the hsync signal with an identical phase shift is available through the hsout pin. phase adjustment is still available if the pixel clock is being provided externally. 4. the 5-bit phase adjust register. the phase of the generated sampling clock may be shifted to locate an optimum sam- pling point within a clock cycle. the phase adjust register the coast allows the pll to continue to run at the same frequency, in the absence of the incoming hsync signal. this may be used during the vertical sync period, or any other time that the hsync signal is unavailable. the polarity of the coast signal may be set through the coast polarity bit. also, the polarity of the hsync signal may be set through the hsync polarity bit. if not using automatic polarity detection, the hsync and coast polarity bits should be set to match the polarity of their respective signals. table vii. recommended vco range and charge pump current settings for standard display formats horizontal refresh frequency pixel rate standard resolution rate (hz) (khz) (mhz) vcornge current vga 640 480 60 31.5 25.175 00 101 72 37.7 31.500 00 101 75 37.5 31.500 00 110 85 43.3 36.000 00 110 svga 800 600 56 35.1 36.000 00 101 60 37.9 40.000 01 101 72 48.1 50.000 01 101 75 46.9 49.500 01 101 85 53.7 56.250 01 110 xga 1024 768 60 48.4 65.000 01 110 70 56.5 75.000 10 101 75 60.0 78.750 10 101 80 64.0 85.500 10 101 85 68.3 94.500 10 101 sxga 1280 1024 60 64.0 108.000 10 110 75 80.0 135.000 11 110 85 91.1 157.500 * 10 110 uxga 1600 1200 60 75.0 162.000 * 10 110 65 81.3 175.500 * 10 110 70 87.5 189.000 * 10 110 75 93.8 202.500 * 10 110 85 106.3 229.500 * 11 110 * graphics sampled at one-half the incoming pixel rate using alternate pixel sampling mode.
rev. 0 ad9887 C17C adc dac dac 7 8 offset gain ref x1.2 in clamp v off 8 figure 8. adc block diagram (single channel output) 1v input range v off (128 codes) input range 0.5v v off (128 codes) offset range 0v 0v offset range figure 9. relationship of offset range to input range scan function the scan function is intended as a pseudo jtag function for manufacturing test of the board. the ordinary operation of the ad9887 is disabled during scan. to enable the scan function, set register 14h, bit 2 to 1. to scan in data to all 48 digital outputs, apply 48 serial bits of data and 48 clocks (typically 5 mhz, max of 20 mhz) to the scan in and scan clk pins respectively. the data is shifted in on the rising edge of scan clk . the first serial bit shifted in will appear at the red a<7> output after one clock cycle. after 48 clocks, the first bit is shifted all the way to the blu b<0>. the 48th bit will now be at the red a<7> output. if scan clk continues after 48 cycles, the data will continue to be shifted from red a<7> to blu b<0> and will come out of the scan out pin as serial data on the falling edge of scan clk . this is illustrated in figure 10. a setup time (t su ) of 3 ns should be plenty and no hold time (t hold ) is required ( 0 ns). this is illustrated in figure 11. t su = 3ns t hold = 0ns scanclk scanin figure 11. scan setup and hold alternate pixel sampling mode a logic 1 input on clock invert (ckinv, pin 94) inverts the nominal adc clock. ckinv can be switched between frames to implement the alternate pixel sampling mode. this allows higher effective image resolution to be achieved at lower pixel rates but with lower frame rates. on one frame, only even pixels are digitized. on the subsequent frame, odd pixels are sampled. by reconstructing the entire frame in the graphics controller, a complete image can be recon- structed. this is very similar to the interlacing process that is employed in broadcast television systems, but the interlacing is vertical instead of horizontal. the frame data is still presented to the display at the full desired refresh rate (usually 60 hz) so no flicker artifacts are added. oeoeoeoeoeoe oeoeoeoeoeoe oeoeoeoeoeoe oeoeoeoeoeoe oeoeoeoeoeoe oeoeoeoeoeoe oeoeoeoeoeoe oeoeoeoeoeoe oeoeoeoeoeoe oeoeoeoeoeoe oeoeoeoeoeoe figure 12. odd and even pixels in a frame o1 o1 o1 o1 o1 o1 o1 o1 o1 o1 o1 o1 o1 o1 o1 o1 o1 o1 o1 o1 o1 o1 o1 o1 o1 o1 o1 o1 o1 o1 o1 o1 o1 o1 o1 o1 o1 o1 o1 o1 o1 o1 o1 o1 o1 o1 o1 o1 o1 o1 o1 o1 o1 o1 o1 o1 o1 o1 o1 o1 o1 o1 o1 o1 o1 o1 figure 13. odd pixels from frame 1 x bit 1 bit 2 x x x bit 1 bit 2 bit 47 bit 48 x bit 46 bit 47 bit 48 x scanclk red a<7> blue b<0> scanout scanin bit 1 bit 2 bit 3 bit 1 bit 2 bit 3 xxx x x x figure 10. scan timing
rev. 0 C18C ad9887 e2 e2 e2 e2 e2 e2 e2 e2 e2 e2 e2 e2 e2 e2 e2 e2 e2 e2 e2 e2 e2 e2 e2 e2 e2 e2 e2 e2 e2 e2 e2 e2 e2 e2 e2 e2 e2 e2 e2 e2 e2 e2 e2 e2 e2 e2 e2 e2 e2 e2 e2 e2 e2 e2 e2 e2 e2 e2 e2 e2 figure 14. even pixels from frame 2 o1e2o1e2o1e2o1e2o1e2o1e2 o1e2o1e2o1e2o1e2o1e2o1e2 o1e2o1e2o1e2o1e2o1e2o1e2 o1e2o1e2o1e2o1e2o1e2o1e2 o1e2o1e2o1e2o1e2o1e2o1e2 o1e2o1e2o1e2o1e2o1e2o1e2 o1e2o1e2o1e2o1e2o1e2o1e2 o1e2o1e2o1e2o1e2o1e2o1e2 o1e2o1e2o1e2o1e2o1e2o1e2 o1e2o1e2o1e2o1e2o1e2o1e2 o1e2o1e2o1e2o1e2o1e2o1e2 figure 15. combine frame output from graphics controller o3e2o3e2o3e2o3e2o3e2o3e2 o3e2o3e2o3e2o3e2o3e2o3e2 o3e2o3e2o3e2o3e2o3e2o3e2 o3e2o3e2o3e2o3e2o3e2o3e2 o3e2o3e2o3e2o3e2o3e2o3e2 o3e2o3e2o3e2o3e2o3e2o3e2 o3e2o3e2o3e2o3e2o3e2o3e2 o3e2o3e2o3e2o3e2o3e2o3e2 o3e2o3e2o3e2o3e2o3e2o3e2 o3e2o3e2o3e2o3e2o3e2o3e2 o3e2o3e2o3e2o3e2o3e2o3e2 figure 16. subsequent frame from controller timing (analog interface) the following timing diagrams show the operation of the ad9887 analog interface in all clock modes. the part estab- lishes timing by having the sample that corresponds to the pixel digitized when the leading edge of hsync occurs sent to the a data port. in dual channel mode, the next sample is sent to the b port. future samples are alternated between the a and b data ports. in single channel mode, data is only sent to the a data port, and the b port is placed in a high impedance state. the output data clock signal is created so that its rising edge always occurs between a data transitions, and can be used to latch the output data externally. pxlclk any output signal datack (output) t skew t dcycle t per data out figure 17. analog output timing hsync timing horizontal sync is processed in the ad9887 to eliminate ambiguity in the timing of the leading edge with respect to the phase-delayed pixel clock and data. the hsync input is used as a reference to generate the pixel sampling clock. the sampling phase can be adjusted, with re spect to hsync, through a full 360 in 32 steps via the phase adjust register (to optimize the pixel sampling time). display systems use hsync to align memory and display write cycles, so it is important to have a stable timing relationship between hsync output (hsout) and data clock (datack). three things happen to horizontal sync in the ad9887. first, the polarity of hsync input is determined and will thus have a known output polarity. the known output polarity can be pro- grammed either active high or active low (register 04h, bit 4). second, hsout is aligned with datack and data outputs. third, the duration of hsout (in pixel clocks) is set via regis- ter 07h. hsout is the sync signal that should be used to drive the rest of the display system. coast timing in most computer systems, the hsync signal is provided con- tinuously on a dedicated wire. in these systems, the coast input and function are unnecessary, and should not be used. in some systems, however, hsync is disturbed during the verti- cal sync period (vsync). in some cases, hsync pulses disappear. in other systems, such as those that employ composite sync (csync) signals or embed sync-on-green (sog), hsync includes equalization pulses or other distortions during vsync. to avoid upsetting the clock generator during vsync, it is important to ignore these distortions. if the pixel clock pll sees extraneous pulses, it will attempt to lock to this new frequency, and will have changed frequency by the end of the vsync period. it will then take a few lines of correct hsync timing to recover at the beginning of a new frame, resulting in a tearing of the image at the top of the display. the coast input is provided to eliminate this problem. it is an asynchronous input that disables the pll input and allows the clock to free-run at its then-current frequency. the pll can free-run for several lines without signi?cant frequency drift. coast can be provided by the graphics controller or it can be internally generated by the ad9887 sync processing engine.
rev. 0 ad9887 C19C p0 p1 p2 p3 p4 p5 p6 p7 5-pipe delay d0 d1 d2 d3 d4 d5 d6 d7 rgb in hsync pxck hs adcck datack d outa hsout figure 18. single channel mode (analog interface) 5-pipe delay d0 d2 d4 d6 p0 p1 p2 p3 p4 p5 p6 p7 rgb in hsync pxck hs adcck datack d outa hsout figure 19. single channel mode, 2 pixels/clock (even pixels) (analog interface) 5.5-pipe delay d1 d3 d5 d7 p0 p1 p2 p3 p4 p5 p6 p7 rgb in hsync pxck hs adcck datack d outa hsout figure 20. single channel mode, 2 pixels/clock (odd pixels) (analog interface)
rev. 0 C20C ad9887 p0 p1 p2 p3 p4 p5 p6 p7 3-pipe delay d0 d2 d4 d6 d1 d3 d5 rgb in hsync pxck hs adcck datack d outa hsout d outb d7 figure 21. dual channel mode, interleaved outputs (analog interface), outphase = 1 p0 p1 p2 p3 p4 p5 p6 p7 7-pipe delay d0 d2 d4 d6 rgb in hsync pxck hs adcck datack d outa hsout d outb d1 d3 d5 d7 figure 22. dual channel mode, parallel outputs (analog interface), outphase = 1 3-pipe delay p0 p1 p2 p3 p4 p5 p6 p7 d4 d2 d6 rgb in hsync pxck hs adcck datack d outa hsout d outb d0 figure 23. dual channel mode, interleaved outputs, 2 pixels/clock (even pixels) (analog interface), outphase = 1
rev. 0 ad9887 C21C 5-pipe delay d1 d5 d3 d7 p0 p1 p2 p3 p4 p5 p6 p7 rgb in hsync pxck hs adcck datack d outa hsout d outb figure 24. dual channel mode, interleaved outputs, 2 pixels/clock (odd pixels) (analog interface), outphase = 1 7-pipe delay p0 p1 p2 p3 p4 p5 p6 p7 d0 d4 d2 d6 rgb in hsync pxck hs adcck datack d outa d outb hsout figure 25. dual channel mode, parallel outputs, 2 pixels/clock (even pixels) (analog interface), outphase = 1 7.5-pipe delay p0 p1 p2 p3 p4 p5 p6 p7 d1 d5 d3 d7 rgb in hsync pxck hs adcck datack d outa d outb hsout figure 26. dual channel mode, parallel outputs, 2 pixels/clock (odd pixels) (analog interface), outphase = 1
rev. 0 C22C ad9887 6-pipe delay p0 p1 p2 p3 p4 p5 p6 p7 u0 v2 u4 v4 u6 rgbin hsync pxck hs adcck datack routa hsout y0 y1 y2 y3 y4 y5 y6 gouta v0 u2 v6 figure 27. 4:2:2 output mode table viii. digital interface pin list pin type pin name function value pin no. digital video data inputs rx0+ digital input channel 0 true 62 rx0C digital input channel 0 complement 63 rx1+ digital input channel 1 true 59 rx1C digital input channel 1 complement 60 rx2+ digital input channel 2 true 56 rx2C digital input channel twos complement 57 digital video clock inputs rxc+ digital data clock true 65 rxcC digital data clock complement 66 termination control r term control pin for setting the internal 53 termination resistance outputs de data enable 3.3 v cmos 137 hsync hsync output 3.3 v cmos 139 vsync vsync output 3.3 v cmos 138 ctl0, ctl1, decoded control bit outputs 3.3 v cmos 46C49 ctl2, ctl3 power supply v d main power supply 3.3 v 5% pv d pll power supply 3.3 v 5% v dd output power supply 3.3 v or 2.5 v 5% gnd ground supply 0 v gnd ground supply 0 v
rev. 0 ad9887 C23C digital interface pin descriptions digital video data inputs rx0+ positive differential input video data (channel 0) rx0C negative differential input video data (channel 0) rx1+ positive differential input video data (channel 1) rx1C negative differential input video data (channel 1) rx2+ positive differential input video data (channel 2) rx2C negative differential input video data (channel 2) these six pins receive three pairs of differential, low voltage swing input pixel data from a digital graphics transmitter. digital video clock inputs rxc+ positive differential input video clock rxcC negative differential input video clock these two pins receive the differential, low voltage swing input pixel clock from a digital graphics transmitter. termination control r term internal termination set pin this pin is used to set the termination resistance for all of the digital interface high-speed inputs. to set, place a resistor of value equal to 10 the desired input termination resistance between this pin (pin 53) and ground supply. typically, the value of this resistor should be 500 ? . outputs de data enable output this pin outputs the state of data enable, (de). the ad9887 decodes de from the incoming stream of data. the de signal will be high dur- ing active video and will be low while there is no active video. power supply v d main power supply it should be as quiet and as ?ltered as possible. pv d pll power supply it should be as quiet and as ?ltered as possible. v dd outputs power supply the power for the data and clock outputs. it can run at 3.3 v or 2.5 v. theory of operation (digital interface) capturing of the encoded data the ?rst step in recovering the encoded data is to capture the raw data. to accomplish this, the ad9887 employs a high-speed phase locked loop (pll), to generate clocks capable of oversampling the data at the correct frequencies. the data capture circuitry continuously monitors the incoming data during horizontal and vertical blanking times (when de is low), and independently selects the best sampling phase for each data channel. the phase information is stored and used until the next blanking period (one video line). data frames the digital interface data is captured in groups of 10 bits each, called a data frame. during the active data period, each frame is made up the nine encoded video data bits and one dc balancing bit. the data capture block receives this data serially, but out- puts each frame in parallel 10-bit words. special characters during periods of horizontal or vertical blanking time (when de is low), the digital transmitter will transmit special characters. the ad9887 will receive these characters and use them to set the video frame boundaries and the phase recovery loop for each channel. there are four special ch aracters that can be received. they are used to identify the top, bottom, left side, and right side of each video frame. the data receiver can differentiate these special characters from active data because the special characters have a different number of transitions per data frame. channel resynchronization the purpose of the channel resynchronization block is to resyn- chronize the three data channels to a single internal data clock. coming into this block, all three data channels can be on differ- ent phases of the three times oversampling pll clock (0 , 120 , and 240 ). this block can resynchronize the channels from a worst-case skew of one full input period (8.93 ns at 112 mhz). data decoder the data decoder receives frames of data and sync signals from the data capture block (in 10-bit parallel words), and decodes them into groups of eight rgb/yuv bits, two control bits, and a data enable bit (de).
rev. 0 C24C ad9887 general timing diagrams (digital interface) 80% 80% 20% 20% d lht d lht figure 28. digital output rise and fall time t cih , r cih t cip , r cip t cil , r cil figure 29. clock cycle/high/low times v diff = 0v t ccs v diff = 0v r x0 r x1 r x2 figure 30. channel-to-channel skew timing datack (internal) datack (pin) t skew data out figure 31. dvi output timing timing mode diagrams (digital interface) first pixel second pixel third pixel fourth pixel internal odclk datack de qe[23:0] qo[23:0] t st figure 32. 1 pixel per clock (datack inverted) first pixel second pixel third pixel fourth pixel internal odclk datack de qe[23:0] qo[23:0] t st figure 33. 1 pixels per clock (datack inverted) first pixel second pixel third pixel fourth pixel internal odclk datack de qe[23:0] qo[23:0] t st figure 34. 2 pixel per clock first pixel second pixel third pixel fourth pixel internal odclk datack de qe[23:0] qo[23:0] t st figure 35. 2 pixels per clock (datack inverted)
rev. 0 ad9887 C25C 2-wire serial register map the ad9887 is initialized and controlled by a set of registers, which determine the operating m odes. an external controller is employed to write and read the control registers through the 2-line serial interface port. table ix. control register map read and hex write or default register address read only bits value name function 00h ro 7:0 chip revision bits 7 through 4 represent functional revisions to the analog interface. bits 3 through 0 represent nonfunctional related revisions. revision 0 = 0000 0000 01h r/ w 7:0 01101001 pll div msb this register is for bits [11:4] of the pll divider. larger values mean the pll operates at a faster rate. this register should be loaded ?rst whenever a change is needed. (this will give the pll more time to lock.) see note 1. 02h r/ w 7:4 1101 **** pll div lsb bits [7:4] lsbs of the pll divider word. see note 1. 03h r/ w 7:2 1 ******* vco/cpmp bit 7must be set to 1 for proper device operation. * 01 ***** bits [6:5] vco range. selects vco frequency range. (see pll description.) *** 001 ** bits [4:2] charge pump current. varies the current that drives the low-pass ?lter. (see pll description.) 04h r/ w 7:3 10000 *** phase adjust adc clock phase adjustment. larger values mean more delay. (1 lsb = t/32) 05h r/ w 7:0 10000000 clamp pl aces the clamp signal an integer number of clock periods after the trail- placement ing edge of the hsync signal. 06h r/ w 7:0 10000000 clamp number of clock periods that the clamp signal is actively clamping. duration 07h r/ w 7:0 00100000 hsync output sets the number of pixel clocks that hsout will remain active. pulsewidth 08h r/ w 7:0 10000000 red gain controls adc input range (contrast) of each respective channel. bigger values give less contrast. 09h r/ w 7:0 10000000 green gain 0ah r/ w 7:0 10000000 blue gain 0bh r/ w 7:1 1000000 * red offset controls dc offset (brightness) of each respective channel. bigger values decrease brightness. 0ch r/ w 7:1 1000000 * green offset 0dh r/ w 7:1 1000000 * blue offset 0eh r/ w 7:3 1 ******* mode bit 7channel mode. determines single channel or dual channel control 1 output mode. (logic 0 = single channel mode, logic 1 = dual channel mode.) * 1 ****** bit 6output mode. determine interleaved or parallel output mode. (logic 0 = interleaved mode, logic 1 = parallel mode.) ** 0 ***** bit 5outphase. determines which port outputs the ?rst data byte after hsync. (logic 0 = b port, logic 1 = a port.) *** 0 **** bit 4hsync output polarity. (logic 0 = logic high sync, logic 1 = logic low sync.) **** 0 *** bit 3vsync output invert. (logic 0 = invert, logic 1 = no invert.)
rev. 0 C26C ad9887 table ix. control register map (continued) read and hex write or default register address read only bits value name function 0fh r/ w 7:0 1 ******* pll and bit 7hsync polarity. indicates the polarity of incoming hsync clamp control signal to the pll. (logic 0 = active low, logic 1 = active high.) * 1 ****** bit 6coast polarity. changes polarity of external coast signal. (logic 0 = active low, logic 1 = active high.) ** 0 ***** bit 5clamp function. chooses between hsync for clamp signal or another external signal to be used for clamping. (lo gic 0 = hsync, logic 1 = clamp.) *** 1 **** bit 4clamp polarity. valid only with external clamp signal. (logic 0 = active low, logic 1 selects active high.) **** 0 *** bit 3extclk. shuts down the pll and allows the use of an external clock to drive the part. (logic 0 = use internal pll, logic 1 = bypass- ing of the internal pll.) ***** 0 ** bit 2red clamp selectlogic 0 selects clamp to ground. logic 1 selects clamp to midscale (voltage at pin 120). ****** 0 * bit 1green clamp selectlogic 0 selects clamp to ground. logic 1 selects clamp to midscale (voltage at pin 111). ******* 0 bit 0blue clamp selectlogic 0 selects clamp to ground. logic 1 selects clamp to midscale (voltage at pin 101). 10h r/ w 7:2 0 ******* mode bit 7clk inv: data clock output invert. (logic 0 = not inverted, control 2 logic 1 = inverted.) (digital interface only.) * 0 ****** bit 6pix select: selects either 1 or 2 pixels per clock mode. (logic 0 = 1 pixel/cl ock, logic 1 = 2 pixels/cloc k.) (digital interface only.) ** 11 **** bit 5, 4output drive: selects between high, medium, and low output drive strength. (logic 11 or 10 = high, 01 = medium, and 00 = low.) **** 0 *** bit 3p do : high impedance outputs. (logic 0 = normal, logic 1 = high impedance.) ***** 1 ** bit 2sync detect (syncdt) polarity. this bit sets the polarity for the syncdt output pin. (logic 1 = active high, logic 0 = active low.) 11h ro 7:1 sync detect/ bit 7analog interface hsync detect. it is set to logic 1 if hsync active is present on the analog interface; otherwise it is set to logic 0. interface bit 6analog interface sync-on-green detect. it is set to logic 1 if sync is present on the green video input; otherwise it is set to 0. bit 5analog interface vsync detect. it is set to logic 1 if vsync is present on the analog interface; otherwise it is set to logic 0. bit 4digital interface clock detect. it is set to logic 1 if the clock is present on the digital interface; otherwise it is set to logic 0. bit 3ai: active interface. this bit indicates which interface is active. (logic 0 = analog interface, logic 1 = digital interface.) bit 2ahs: active hsync. this bit indicates which analog h sync is being used. (logic 0 = hsync input pin, logic 1 = hsync from sync-on-green.) bit 1avs: active vsync. this bit indicates which analog v sync is being used. (logic 0 = vsync input pin, logic 1 = vsync from sync separator.)
rev. 0 ad9887 C27C table ix. control register map (continued) read and hex write or default register address read only bits value name function 12h r/ w 7:0 0 ******* active bit 7aio: active interface override. if set to logic 1, the user interface can select the active interface via bit 6. if set to logic 0, the active interface is selected via bit 3 in register 11h. * 0 ****** bit 6ais: active interface select. logic 0 s elects the analog inter- face as active. logic 1 selects the digital interface as active. note: the indicated interface will be active only if bit 7 is set to logic 1 or if both interfaces are active (bits 6 or 7 and 4 = logic 1 in register 11h.) ** 0 ***** bit 5active hsync override. if set to logic 1, the user can select the hsync to be used via bit 4. if set to logic 0, the active interface is selected via bit 2 in register 11h. *** 0 **** bit 4active hsync select. logic 0 selects hsync as the active sync. logic 1 selects sync-on-green as the active sync. note: the indicated hsync will be used only if bit 5 is set to logic 1 or if both syncs are active (bits 6, 7 = logic 1 in register 11h.) **** 0 *** bit 3active vsync override. if set to logic 1, the user can select the vsync to be used via bit 2. if set to logic 0, the active interface is selected via bit 1 in register 11h. ***** 0 ** bit 2active vsync select. logic 0 selects raw vsync as the output vsync. logic 1 selects sync separated vsync as the output vsync. note: the indicated vsync will be used only if bit 3 is set to logic 1. ****** 0 * bit 1coast select. logic 0 selects the coast input pin to be used for the pll coast. logic 1 selects vsync to be used for the pll coast. ******* 1 bit 0 pwrdn . full chip power-down, active low. (logic 0 = full chip power-down, logic 1 = normal.) 13h r/ w 7:0 00100000 sync sync separator thresholdsets the number of clocks the sync separator separator will count to before toggling high or low. this should be threshold set to some number greater than the maximum hsync or equaliza- tion pulsewidth. 14h r/ w 7:0 *** 1 **** control bits bit 4must be set to 1 for proper operation. **** 0 *** bit 3must be set to 0 for proper operation. ***** 0 ** bit 2scan enable. (logic 0 = not enabled, logic 1 = enabled.) ****** 0 * bit 1coast polarity override. (logic 0 = polarity determined by chip, logic 1 = polarity set by bit 6 in register 0fh.) ******* 0 bit 0hsync polarity override. (logic 0 = polarity determined by chip, logic 1 = polarity set by bit 7 in register 0fh.) 15h ro 7:5 polarity status bit 7hsync input polarity status. (logic 1 = active high, logic 0 = active low.) bit 6vsync output polarity status. (logic 0 = active high, logic 1 = active low.) bit 5coast input polarity status. (logic 1 = active high, logic 0 = active low.) 16h r/ w 7:2 10111*** control bits 2 bits [7:3]sync-on-green slicer threshold ******1* bit 1must be set to 0 for proper operation. 17h r/ w 7:0 00000000 pre-coast sets the number of hsyncs that coast goes active prior to vsync. 18h r/ w 7:0 00000000 post-coast sets the number of hsyncs that coast goes active following vsync. 19h r/ w 7:0 00000000 test register must be set to default for proper operation. 1ah r/ w 7:0 11111111 test register must be set to 01000001 for proper operation.
rev. 0 C28C ad9887 read and hex write or default register address read only bits value name function 1bh r/ w 7:0 00000000 test register must be set to 00010000 for proper operation. 1ch r/ w 7:0 000001** 4:2:2 control bits [7:2]must be set to 011011** for proper operation. ******1* bit 1must be set to default for proper operation. ******* 1 bit 0output format mode select logic 1 = 4:4:4 mode logic 0 = 4:2:2 mode 1dh ro 7:0 test register reserved for future use. 1eh ro 7:0 test register reserved for future use. 1fh ro 7:0 test register reserved for future use. note 1 the ad9887 only updates the pll divide ratio when the lsbs are written to (register 02h). table ix. control register map (continued)
rev. 0 ad9887 C29C 2-wire serial control register detail chip identification 00 7? chip revision bits 7 through 4 represent functional revisions to the analog interface. changes in these bits will generally indicate that software and/or hardware changes will be required for the chip to work properly. bits 3 through 0 represent nonfunctional related revisions and are reset to 0000 whenever the msbs are changed. changes in these bits are considered transparent to the user. pll divider control 01 7? pll divide ratio msbs the eight most signi?cant bits of the 12-bit pll divide ratio plldiv. (the operational divide ratio is plldiv + 1.) the pll derives a pixel clock from the incoming hsync signal. the pixel clock frequency is then divided by an integer value, such that the output is phase-locked to hsync. this plldiv value determines the number of pixel times (pixels plus horizontal blanking overhead) per line. this is typically 20% to 30% more than the number of active pixels in the display. the 12-bit value of the pll divider supports divide ratios from 221 to 4095. the higher the value loaded in this register, the higher the resulting clock frequency with respect to a ?xed hsync frequency. vesa has established some standard timing speci?ca tions, which will assist in determining the value for plldiv as a function of horizontal and vertical display resolution and frame rate (table vii). however, many computer systems do not conform pre- cisely to the recommendations, and these numbers should be used only as a guide. the display system manufacturer should provide automatic or manual means for optimizing plldiv. an incorrectly set plldiv will usually produce one or more vertical noise bars on the display. the greater the error, the greater the number of bars produced. the power-up default value of plldiv is 1693 (plldivm = 69h, plldivl = dxh). the ad9887 updates the full divide ratio only when the lsbs are changed. writing to this register by itself will not trigger an update. 02 7? pll divide ratio lsbs the four least signi?cant bits of the 12-bit pll divide ratio plldiv. the operational divide ratio is plldiv + 1. the power-up default value of plldiv is 1693 (plldivm = 69h, plldivl = dxh). the ad9887 updates the full divide ratio only when this register is written. clock generator control 03 7 test set to one 03 6? vco range select two bits that establish the operating range of the clock generator. vcornge must be set to correspond with the desired operating frequency (incoming pixel rate). the pll gives the best jitter performance at high fre- quencies. for this reason, in order to output low pixel rates and still get good jitter performance, the pll actu- ally operates at a higher frequency but then divides down the clock rate afterwards. table x shows the pixel rates for each vco range setting. the pll output divisor is automatically selected with the vco range setting. table x. vco ranges vcornge pixel rate range 00 12C35 01 35C70 10 70C110 11 110C140 the power-up default value is = 01. 03 4? current charge pump current three bits that establish the current driving the loop ?lter in the clock generator. table xi. charge pump currents current current ( a) 000 50 001 100 010 150 011 250 100 350 101 500 110 750 111 1500 see table vii for the recommended current settings. the power-up default value is current = 001. 04 7? clock phase adjust a ?ve-bit value that adjusts the sampling phase in 32 steps across one pixel time. each step represents an 11.25 shift in sampling phase. the power-up default value is 16. clamp timing 05 7? clamp placement an eight-bit register that sets the position of the internally generated clamp. when extclmp = 0, a clamp signal is generated inter- nally, at a position established by the clamp placement and for a duration set by the clamp duration. clamping is started (clamp placement) pixel periods after the trailing edge of hsync. the clamp placement may be programmed to any value between 1 and 255. a value of 0 is not supported. the clamp should be placed during a time that the input signal presents a stable black-level reference, usually the back porch period between hsync and the image. when extclmp = 1, this register is ignored.
rev. 0 C30C ad9887 06 7? clamp duration an 8-bit register that sets the duration of the internally generated clamp. when extclmp = 0, a clamp signal is generated inter- nally, at a position established by the clamp placement and for a duration set by the clamp duration. clamping is started (clamp placement) pixel periods after the trailing edge of hsync, and continues for (clamp duration) pixel periods. the clamp duration may be programmed to any value between 1 and 255. a value of 0 is not supported. for the best results, the clamp duration should be set to include the majority of the black reference signal time that follows the hsync signal trailing edge. insuf?cient clamp- ing time can produce brightness changes at the top of the screen, and a slow recovery from large changes in the average picture level (apl), or brightness. when extclmp = 1, this register is ignored. hsync pulsewidth 07 7? hsync output pulsewidth an 8-bit register that sets the duration of the hsync output pulse. the leading edge of the hsync output is triggered by the internally generated, phase-adjusted pll feedback clock. the ad9887 then counts a number of pixel clocks equal to the value in this register. this triggers the trailing edge of the hsync output, which is also phase-adjusted. input gain 08 7? red channel gain adjust an 8-bit word that sets the gain of the red channel. the ad9887 can accommodate input signals with a full-scale range of between 0.5 v and 1.5 v p-p. setting redgain to 255 corre sponds to an in put range of 1.0 v. a redgain of 0 establishes an input range of 0.5 v. note that increasing redgain results in the pic ture having less contrast (the input signal uses fewer of the available converter codes). see figure 3. 09 7? green channel gain adjust an 8-bit word that sets the gain of the green channel. see redgain (08). 0a 7? blue channel gain adjust an 8-bit word that sets the gain of the blue channel. see redgain (08). input offset 0b 7? red channel offset adjust a 7-bit offset binary word that sets the dc offset of the red channel. one lsb of offset adjustment equals approxim ately one lsb change in the adc offset. therefore, the abso lute magnitude of the offset adjustment scales as the gain of the channel is changed. a nominal setting of 63 results in the channel nominally clamping the back porch (during the clamping interval) to code 00. an offset setting of 127 results in the channel clamping to code 63 of the adc. an offset setting of 0 clamps to code C63 (off the bottom of the range). increasing the value of red offset decreases the brightness of the channel. 0c 7? green channel offset adjust a 7-bit offset binary word that sets the dc offset of the green channel. see redofst (0b). 0d 7? blue channel offset adjust a 7-bit offset binary word that sets the dc offset of the green channel. see redofst (0b). mode control 1 0e 7 channel mode a bit that determines whether all pixels are presented to a single port (a), or alternating pixels are demultiplexed to ports a and b. table xii. channel mode settings demux function 0 all data goes to port a 1 alternate pixels go to port a and port b when demux = 0, port b outputs are in a high-impedance state. the maximum data rate for single port mode is 100 mhz. the timing diagrams show the effects of this option. the power-up default value is 1. 0e 6 output mode a bit that determines whether all pixels are presented to port a and port b simultaneously on every second datack rising edge, or alternately on port a and port b on successive datack rising edges. table xiii. output mode settings parallel function 0 data is interleaved 1 data is simultaneous on every other data clock when in single port mode (demux = 0), this bit is ig- nored. the timing diagrams show the effects of this option. the power-up default value is parallel = 1. 0e 5 output port phase one bit that determines whether even pixels or odd pixels go to port a. table xiv. output port phase settings outphase first pixel after hsync 0 port b 1 port a in normal operation (outphase = 1), when operating in dual-port output mode (demux = 1), the ?rst sample after the hsync leading edge is presented at port a. every subsequent odd sample appears at port a. all even samples go to port b. when outphase = 0, these ports are reversed and the ?rst sample goes to port b.
rev. 0 ad9887 C31C when demux = 0, this bit is ignored as data always comes out of only port a. 0e 4 hsync output polarity one bit that determines the polarity of the hsync out- put and the sog output. table xv shows the effect of this option. sync indicates the logic state of the sync pulse. table xv. hsync output polarity settings setting sync 0 logic 1 (positive polarity) 1 logic 0 (negative polarity) the default setting for this register is 1. (this option works on both the analog and digital interfaces.) 0e 3 vsync output invert one bit that inverts the polarity of the vsync output. table xvi shows the effect of this option. table xvi. vsync output polarity settings setting vsync output 0 invert 1 no invert the default setting for this register is 1. (this option works on both the analog and digital interfaces.) 0f 7 hsync input polarity a bit that must be set to indicate the polarity of the hsync signal that is applied to the pll hsync input. table xvii. hsync input polarity settings hspol function 0 active low 1 active high active low is the traditional negative-going hsync pulse. all timing is based on the leading edge of hsync, which is the falling edge. the rising edge has no effect. active high is inverted from the traditional hsync, with a positive-going pulse. this means that timing will be based on the leading edge of hsync, which is now the rising edge. the device will operate if this bit is set incorrectly, but the internally generated clamp position, as established by clpos, will not be placed as expected, which may gener- ate clamping errors. the power-up default value is hspol = 1. 0f 6 coast input polarity a bit to indicate the polarity of the coast signal that is applied to the pll coast input. table xviii. coast input polarity settings cstpol function 0 active low 1 active high active low means that the clock generator will ignore hsync inputs when coast is low, and continue operating at the same nominal frequency until coast goes high. active high means that the clock generator will ignore hsync inputs when coast is high, and continue operat- ing at the same nominal frequency until coast goes low. this function needs to be used along with the coast polarity override bit (register 14, bit 1). the power-up default value is cstpol = 1. 0f 5 clamp input signal source a bit that determines the source of clamp timing. table xix. clamp input signal source settings extclmp function 0 internally-generated clamp 1 externally-provided clamp signal a 0 enables the clamp timing circuitry controlled by clplace and cldur. the clamp position and dura- tion is counted from the leading edge of hsync. a 1 enables the external clamp input pin. the three channels are clamped when the clamp signal is active. the polarity of clamp is determined by the clampol bit. the power-up default value is extclmp = 0. 0f 4 clamp input signal polarity a bit that determines the polarity of the externally pro- vided clamp signal. table xx. clamp input signal polarity settings extclmp function 0 active low 1 active high a logic 0 means that the circuit will clamp when clamp is high, and it will pass the signal to the adc when clamp is low. a logic 1 means that the circuit will clamp when clamp is low, and it will pass the signal to the adc when clamp is high. the power-up default value is clampol = 1. 0f 3 external clock select a bit that determines the source of the pixel clock. table xxi. external clock select settings extclk function 0 internally generated clock 1 externally provided clock signal a logic 0 enables the internal pll that generates the pixel clock from an externally provided hsync.
rev. 0 C32C ad9887 a logic 1 enables the external ckext input pin. in this mode, the pll divide ratio (plldiv) is ignored. the clock phase adjust (phase) is still functional. the power-up default value is extclk = 0. 0f 2 red clamp select a bit that determines whether the red channel is clamped to ground or to midscale. for rgb video, all three chan- nels are referenced to ground. for ycbcr (or yuv), the y channel is referenced to ground, but the cbcr channels are referenced to midscale. clamping to midscale actually clamps to pin 118, r clamp v. table xxii. red clamp select settings clamp function 0 clamp to ground 1 clamp to midscale (pin 118) the default setting for this register is 0. 0f 1 green clamp select a bit that determines whether the green channel is clamped to ground or to midscale. table xxiii. green clamp select settings clamp function 0 clamp to ground 1 clamp to midscale (pin 109) the default setting for this register is 0. 0f 0 blue clamp select a bit that determines whether the blue channel is clamped to ground or to midscale. table xxiv. blue clamp select settings clamp function 0 clamp to ground 1 clamp to midscale (pin 99) the default setting for this register is 0. mode control 2 10 7 clk inv data output clock invert a control bit for the inversion of the output data clocks, (pins 134, 135). this function works only for the digital interface. when not inverted, data is output on the rising edge of the data clock. see timing diagrams to see how this affects timing. table xxv. clock output invert settings clk inv function 0 not inverted 1 inverted the default for this register is 0, not inverted. 10 6 pix select this bit selects either 1 or 2 pixels per clock mode for the digital interface. it determines whether the data comes out of a single port (even port only), at the full data rate or out of two ports (both even and odd ports), at one-half the full data rate per port. a logic 0 selects 1 pixel per clock (even port only). a logic 1 selects 2 pixels per clock (both ports). see the digital interface timing diagrams, figures 29 to 32, for a visual representation of this func tion. note: this function operates exactly like the demux function on the analog interface. table xxvi. pix select settings pix select function 0 1 pixel per clock 1 2 pixels per clock the default for this register is 0, 1 pixel per clock. 10 5, 4 output drive these two bits select the drive strength for the high-speed digital outputs (all data output and clock output pins). higher drive strength results in faster rise/fall times and in general makes it easier to capture data. lower drive strength results in slower rise/fall times and helps to reduce emi and digitally generated power supply noise. the exact timing speci?cations for each of these modes are speci?ed in table vii. table xxvii. output drive strength settings bit 5 bit 4 result 1 1 high drive strength 1 0 medium drive strength 0 x low drive strength the default for this register is 11, high drive strength. (this option works on both the analog and digital interfaces.) 10 3 p do ?ower-down outputs a bit that can put the outputs in a high impedance mode. this applies only to the 48 data output pins and the two data clock output pins. table xxviii. power-down output settings ckinv function 0 normal operation 1 three-state the default for this register is 0. (this option works on both the analog and digital interfaces.) 10 2 sync detect polarity this pin controls the polarity of the sync detect output pin (pin 136). table xxix. sync detect polarity settings polarity function 0 activity = logic 1 output 1 activity = logic 0 output the default for this register is 0. (this option works on both the analog and digital interfaces.)
rev. 0 ad9887 C33C sync detection and control 11 7 analog interface hsync detect this bit is used to indicate when activity is detected on the hsync input pin (pin 82). if hsync is held high or low, activity will not be detected. table xxx. hsync detection results detect function 0 no activity detected 1 activity detected figure 38 shows where this function is implemented. 11 6 analog interface sync-on-green detect this bit is used to indicate when sync activity is detected on the sync-on-green input pin (pin 108). table xxxi. sync-on-green detection results detect function 0 no activity detected 1 activity detected figure 38 shows where this function is implemented. warning: if no sync is present on the green video input, normal video may still trigger activity. 11 5 analog interface vsync detect this bit is used to indicate when activity is detected on the vsync input pin (pin 81). if vsync is held high or low, activity will not be detected. table xxxii. vsync detection results detect function 0 no activity detected 1 activity detected figure 38 shows where this function is implemented. 11 4 digital interface clock detect this bit is used to indicate when activity is detected on the digital interface clock input. table xxxiii. digital interface clock detection results detect function 0 no activity detected 1 activity detected the sync processing block diagram shows where this function is implemented. 11 3 active interface this bit is used to indicate which interface should be active, analog, or digital. it checks for activity on the analog interface and for activity on the digital interface, then determines which should be active according to table xxxiv. speci?cally, analog interface detection is determined by or-ing bits 7, 6, and 5 in this register. digital interface detection is determined by bit 4 in this register. if both interfaces are detected, the user can determine which has priority via bit 6 in register 12h. the user can override this function via bit 7 in register 12h. if the override bit is set to logic 1, then this bit will be forced to whatever the state of bit 6 in register 12h is set to. table xxxiv. active interface results bits 7, 6, or 5 bit 4 (analog (digital detection) detection) override ai 000soft power-down (seek mode) 0101 1000 1 1 0 bit 6 in 12h x x 1 bit 6 in 12h ai = 0 means analog interface. ai = 1 means digital interface. the override bit is in register 12h, bit 7. 11 2 ahs?ctive hsync this bit is used to determine which hsync should be used for the analog interface, the hsync input or sync- on-green. it uses bits 7 and 6 in this register for inputs in determining which should be active. similar to the previ- ous bit, if both hsync and sog are detected the user can determine which has priority via bit 4 in register 12h. the user can override this function via bit 5 in register 12h. if the override bit is set to logic 1, this bit will be forced to whatever the state of bit 4 in register 12h is set to. table xxxv. active hsync results bit 7 bit 6 (hsync (sog detect) detect) override ahs 0 0 0 bit 4 in 12h 0 101 1 000 1 1 0 bit 4 in 12h x x 1 bit 4 in 12h ahs = 0 means use the hsync pin input for hsync. ahs = 1 means use the sog pin input for hsync. the override bit is in register 12h, bit 5. 11 1 avs?ctive vsync this bit is used to determine which vsync should be used for the analog interface; the vsync input or output from the sync separator. if both vsync and composite sog are detected, vsync will be selected. the user can override this function via bit 3 in register 12h. if the override bit is set to logic 1, this bit will be forced to what- ever the state of bit 2 in r egister 12h is set to.
rev. 0 C34C ad9887 table xxxvi. active vsync results bit 5 (vsync detect) override avs 00 0 10 1 x 1 bit 2 in 12h avs = 1 means sync separator. avs = 0 means vsync input. the override bit is in register 12h, bit 3. 12 7 aio?ctive interface override this bit is used to override the automatic interface selec- tion (bit 3 in register 11h). to override, set this bit to logic 1. when overriding, the active interface is set via bit 6 in this register. table xxxvii. active interface override settings aio result 0 autodetermines the active interface 1 override, bit 6 determines the active interface the default for this register is 0. 12 6 ais?ctive interface select this bit is used under two conditions. it is used to select the active interface when the override bit is set (bit 7). alternately, it is used to determine the active interface when not overriding but both interfaces are detected. table xxxviii. active interface select settings ais result 0 analog interface 1 digital interface the default for this register is 0. 12 5 active hsync override this bit is used to override the automatic hsync selection (bit 2 in register 11h). to override, set this bit to logic 1. when overriding, the active hsync is set via bit 4 in this register. table xxxix. active hsync override settings override result 0 autodetermines the active interface 1 override, bit 4 determines the active inter face the default for this register is 0. 12 4 active hsync select this bit is used under two conditions. it is used to select the active hsync when the override bit is set (bit 5). alter- nately, it is used to determine the active hsync when not overriding but both hsyncs are detected. table xl. active hsync select settings select result 0 hsync input 1 sync-on-green input the default for this register is 0. 12 3 active vsync override this bit is used to override the automatic vsync selec tion (bit 1 in register 11h). to override, set this bit to logic 1. when overriding, the active interface is set via bit 2 in this register. table xli. active vsync override settings override result 0 autodetermines the active vsync 1 override, bit 2 determines the active v sync the default for this register is 0. 12 2 active vsync select this bit is used to select the active vsync when the override bit is set (bit 3). table xlii. active vsync select settings select result 0 vsync input 1 sync separator output the default for this register is 0. 12 1 coast select this bit is used to select the active coast source. the choices are the coast input pin or vsync. if vsync is selected, the additional decision of using the vsync input pin or the output from the sync separator needs to be made (bits 3, 2). table xliii. coast select settings select result 0 coast input pin 1 vsync (see above text) the default for this register is 0. 12 0 pwrdn this bit is used to put the chip in full power-down. this powers down both interfaces. see the section on power management for details of which blocks are actually powered down. note, the chip will be unable to detect incoming activity while fully powered-down. table xliv. power-down settings select result 0 power-down 1 normal operation the default for this register is 1.
rev. 0 ad9887 C35C digital control 13 7:0 sync separator threshold this register is used to set the responsiveness of the sync separator. it sets how many pixel clock pulses the sync separator must count to before toggling high or low. it works like a low-pass ?lter to ignore hsync pulses in order to extract the vsync signal. this register should be set to some number greater than the maximum hsync pulsewidth. the default for this register is 32. control bits 14 2 scan enable this register is used to enable the scan function. when enabled, data can be loaded into the ad9887 outputs serially with the scan function. the scan function utilizes three pins (scan in , scan out , and scan clk ). these pins are described in table i. table xlv. scan enable settings scan enable result 0 scan function disabled 1 scan function enabled the default for scan enable is 0 (disabled). 14 1 coast input polarity override this register is used to override the internal circuitry that determines the polarity of the coast signal going into the pll. table xlvi. coast input polarity override settings override bit result 0 coast polarity determined by chip 1 coast polarity determined by user the default for coast polarity override is 0 (polarity determined by chip). 14 0 hsync input polarity override this register is used to override the internal circuitry that determines the polarity of the hsync signal going into the pll. table xlvii. hsync input polarity override settings override bit result 0 hsync polarity determined by chip 1 hsync polarity determined by user the default for hsync polarity override is 0 (polarity determined by chip). 15 7 hsync input polarity status this bit reports the status of the hsync input polarity detection circuit. it can be used to determine the polarity of the hsync input. the detection circuits location is shown in the sync processing block diagram (figure 38). table xlviii. detected hsync i nput polarity status hsync polarity status result 0 hsync polarity is negative. 1 hsync polarity is positive. 15 6 vsync output polarity status this bit reports the status of the vsync output polarity detection circuit. it can be used to determine the polarity of the vsync input. the detection circuits location is shown in the sync processing block diagram (figure 38). table xlix. detected vsync input polarity status vsync polarity status result 0 vsync polarity is active low. 1 vsync polarity is active high. 15 5 coast input polarity status this bit reports the status of the coast input polarity detection circuit. it can be used to determine the polar- ity of the coast input. the detection circuits location is shown in the sync processing block diagram (figure 38). table l. detected coast input polarity status coast polarity status result 0 coast polarity is negative. 1 coast polarity is positive. 16 7? sync-on-green slicer threshold this register allows the comparator threshold of the sync-on-green slicer to be adjusted. this register adjusts the comparator threshold in steps of 10 mv. a setting of zero results in a 330 mv threshold. the setting of 31 results in a 10 mv threshold. the default setting is 23 and corresponds to a threshold value of 70 mv. 17 7? pre-coast this register allows the coast signal to be applied prior to the vsync signal. this is necessary in cases where pre- equalization pulses are present. the step size for this control is one hsync period. the default is 0. 18 7? post-coast this register allows the coast signal to be applied follow- ing to the vsync signal. this is necessary in cases where post-equalization pulses are present. the step size for this control is one hsync period. the default is 0. 19 7? test register must be set to default. 1a 7? test register must be set to 41h for proper operation.
rev. 0 C36C ad9887 1b 7? test register must be set to 10h for proper operation. 1c 7? test bits must be set to 6fh for proper operation. 1c 1 output format mode select a bit that configures the output data in 4:2:2 mode. this mode can be used to reduce the number of data lines used from 24 down to 16 for applications using yuv, ycbcr, or ypbpr graphics signals. a timing diagram for this m ode is shown on page 22. recommended input and output con- figurations are shown in table li. in 4:2:2 mode, the red and blue channels can be interchanged to help satisfy board layout or timing requirements, but the green channel must be configured for y. table li. 4:2:2 output mode select select output mode 1 4:4:4 1 4:2:2 table lii. 4:2:2 input/output configuration input output channel connection format red v u/v green y y blue u high impedance 1c 1? test bits must be set to default. 2-wire serial control port a 2-wire serial interface control interface is provided. up to four ad9887 devices may be connected to the 2-wire serial interface, with each device having a unique address. the 2-wire serial interface comprises a clock (scl) and a bidi- rectional data (sda) pin. the analog flat panel interface acts as a slave for receiving and transmitting data over the serial inter face. when the serial interface is not active, the logic levels on scl and sda are pulled high by external pull-up resistors. data received or transmitted on the sda line must be stable for the duration of the positive-going scl pulse. data on sda must change only when scl is low. if sda changes state while scl is high, the serial interface interprets that action as a start or stop sequence. there are five components to serial bus operation: ? start signal ? slave address byte ? base register address byte ? data byte to read or write ? stop signal when the serial interface is inactive (scl and sda are high) communications are initiated by sending a start signal. the start signal is a high-to-low transition on sda while scl is high. this signal alerts all slaved devices that a data transfer sequence is coming. the ?rst eight bits of data transferred after a start signal comprising a 7-bit slave address (the ?rst seven bits) and a single r/ w bit (the eighth bit). the r/ w bit indicates the direction of data transfer, read from (1) or write to (0) the slave device. if the t ransmitted slave address matches the address of the device (set by the state of the sa 1-0 input pins in table liii, the ad9887 acknowledges by bringing sda low on the 9th scl pulse. if the addresses do not match, the ad 9887 does not acknowledge. table liii. serial port addresses bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 a 6 a 5 a 4 a 3 a 2 a 1 a 0 (msb) 1 001100 1 001101 1 001110 1 001111 data transfer via serial interface for each byte of data read or written, the msb is the ?rst bit of the sequence. if the ad9887 does not acknowledge the master device during a write sequence, the sda remains high so the master can generate a stop signal. if the master device does not acknowledge the ad9887 during a read sequence, the ad9887 interprets this as end of data. the sda remains high so the master can generate a stop signal. writing data to speci?c control registers of the ad9887 requires that the 8-bit address of the control register of interest be written after the slave address has been established. this control register address is the base address for subsequent write operations. the base address autoincrements by one for each byte of data written after the data byte intended for the base address. if more bytes are transferred than there are available addresses, the address will not increment and remain at its maximum value of 1dh. any base address higher than 1dh will not produce an acknowledge signal. data is read from the control registers of the ad9887 in a sim ilar manner. reading requires two data transfer operations: the base address must be written with the r/ w bit of the slave address byte low to set up a sequential read operation. reading (the r/ w bit of the slave address byte high) begins at the previously established base address. the address of the read register autoincrements after each byte is transferred. to terminate a read/write sequence to the ad9887, a stop sig- nal must be sent. a stop signal comprises a low-to-high transition of sda while scl is high. a repeated start signal occurs when the master device driving the serial interface generates a start signal without ?rst generat- ing a stop signal to terminate the current communication. this is used to change the mode of communication (read, write) between the slave and master without releasing the serial inter- face lines. serial interface read/write examples write to one control register ? start signal ? slave address byte (r/ w bit = low) ? base address byte ? data byte to base address ? stop signal
rev. 0 ad9887 C37C write to four consecutive control registers ? start signal ? slave address byte (r/ w bit = low) ? base address byte ? data byte to base address ? data byte to (base address + 1) ? data byte to (base address + 2) ? data byte to (base address + 3) ? stop signal read from one control register ? start signal ? slave address byte (r/ w bit = low) ? base address byte ? start signal ? slave address byte (r/ w bit = high) ? data byte from base address ? stop signal read from four consecutive control registers ? start signal ? slave address byte (r/ w bit = low) ? base address byte ? start signal ? slave address byte (r/ w bit = high) ? data byte from base address ? data byte from (base address + 1) ? data byte from (base address + 2) ? data byte from (base address + 3) ? stop signal bit 7 sda scl ack bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 figure 37. serial interfacetypical byte transfer table liv. control of the sync block muxes via the serial register control mux serial bus bit nos. control bit state result 1 and 2 12h: bit 4 0 pass hsync 1 pass sync-on-green 3 12h: bit 1 0 pass coast 1 pass vsync 4 12h: bit 2 0 pass vsync 1 pass sync separator signal 5, 6, and 7 11h: bit 3 0 pass digital interface signals 1 pass analog interface signals theory of operation (sync processing) this section is devoted to the basic operation of the sync pro cess- ing engine (refer to figure 37 sync processing block diagram). sync slicer the purpose of the sync slicer is to extract the sync signal from the green graphics channel. a sync signal is not present on all graphics systems, only those with sync-on-green. the sync signal is extracted from the green channel in a two step process. first, the sog input is clamped to its negative peak (typically 0.3 v below the black level). next, the signal goes to a compara- tor with a trigger level that is 0.15 v above the clamped level. the sliced sync is typically a composite sync signal containing both hsync and vsync. sync separator a sync separator extracts the vsync signal from a composite sync signal. it does this through a low-pass ?lter-like or integrator- like operation. it works on the idea that the vsync signal stays active for a much longer time than the hsync signal, so it re jects any signal shorter than a threshold value, which is somewhere between an hsync pulsewidth and a vsync pulsewidth. the sync separator on the ad9887 is simply an 8-bit digital counter with a 5 mhz clock. it works independently of the polarity of the composite sync signal. (polarities are determined elsewhere on the chip.) the basic idea is that the counter counts up when hsync pulses are present. but since hsync pulses are relatively short in width, the counter only reaches a value of n before the pulse ends. it then starts counting down eventually reaching 0 before the next hsync pulse arrives. the speci?c value of n will vary for different video modes, but will always be less than 255. for example with a 1 s width hsync, the counter will only reach 5 (1 s/200 ns = 5). now, when vsync is present on the composite sync the counter will also count up. however, since the vsync signal is much longer, it will count to a higher number m. for most video modes, m will be at least 255. so, vsync can be detected on the composite sync signal by detecting when the counter counts to higher than n. the speci?c count that triggers detection (t) can be programmed through the serial register (0fh). once vsync has been detected, there is a similar process to detect when it goes inactive. at detection, the counter ?rst resets to 0, then starts counting up when vsync goes away. similar to the previous case, it will detect the absence of vsync when the counter reaches the threshold count (t). in this way, it will reject noise and/or serration pulses. once vsync is detected to be absent, the counter resets to 0 and begins the cycle again. sda scl t buff t stah t dho t dsu t dal t dah t stasu t stosu figure 36. serial port read/ write timing
rev. 0 C38C ad9887 pcb layout recommendations the ad9887 is a high-performance, high-speed analog device. as such, to get the maximum performance out of the part it is important to have a well laid-out board. the following is a guide for designing a board using the ad9887. analog interface inputs using the following layout techniques on the graphics inputs is extremely important: minimize the trace length running into the graphics inputs. this is accomplished by placing the ad9887 as c lose as possible to the graphics vga connector. long input trace lengths are unde- sirable because they will pick up more noise from the board and other external sources. place the 75 ? termination resistors as close to the ad9887 chip as possible. any additional trace length between the termi- nation resistors and the input of the ad9887 increases the magnitude of reflections, which will corrupt the graphics signal. use 75 ? matched impedance traces. trace impedances other than 75 ? will also increase the chance of reflections. the ad9887 has very high input bandwidth, (330 mhz). while this is desirable for acquiring a high resolution pc graphics signal with fast edges, it means that it will also capture any high frequency noise present. therefore, it is important to reduce the amount of noise that gets coupled to the inputs. avoid running any digital traces near the analog inputs. due to the high bandwidth of the ad9887, sometimes low-pass ?ltering the analog inputs can help to reduce noise. (for many applications, ?ltering is unnecessary.) experiments have shown that placing a series ferrite bead prior to the 75 ? termination resistor is helpful in ?ltering out excess noise. speci?cally, the part used was the # 2508051217z0 from fair-rite, but each application may work best with a different bead value. alternately, placing a 100 ? to 120 ? resistor between the 75 ? termination resistor and the input coupling capacitor can also be beneficial. digital interface inputs each differential input pair (r xo +, r xo C, r xc +, r xc C, etc.) should be routed together using 50 ? strip line routing tech- niques and should be kept as short as possible. no other components should be placed on these inputs; for example, no clamping diodes. every effort should also be made to route these signals on a single layer (component layer) with no vias. power supply bypassing it is recommended to bypass each power supply pin with a 0.1 f capacitor. the exception is in the case where two or more supply pins are adjacent to each other. for these group- ings of powers/grounds, it is only necessary to have one bypass capacitor. the fundamental idea is to have a bypass capacitor within about 0.5 cm of each power pin. also, avoid placing the capacitor on the opposite side of the pc board from the ad9887, as that interposes resistive vias in the path. the bypass capacitors should be physically located between the power plane and the power pin. current should flow from the power plane to the capacitor to the power pin. do not make the power connection between the capacitor and the power pin. placing a via underneath the capacitor pads, down to the power plane, is generally the best approach. sync stripper activity detect negative peak clamp comp sync sog hsync in activity detect mux 2 hsync out pixel clock mux 1 sync separator integrator vsync sog out hsync out vsync out mux 4 vsync in 1/s pll hsync activity detect ad9887 clock generator polarity detect polarity detect polarity detect mux 3 coast coast figure 38. sync processing block diagram
rev. 0 ad9887 C39C it is particularly important to maintain low noise and good stability of pv d (the clock generator supply). abrupt changes in pv d can result in similarly abrupt changes in sampling clock phase and frequency. this can be avoided by careful attention to regulation, ?ltering, and bypassing. it is highly desirable to provide separate regulated supplies for each of the analog cir- cuitry groups (v d and pvd). some graphic controllers use substantially different levels of power when active (during active picture time) and when idle (during horizontal and vertical sync periods). this can result in a measurable change in the voltage supplied to the analog supply regulator, which can in turn produce changes in the regulated analog supply voltage. this can be mitigated by regu- lating the analog supply, or at least pv d , from a different, cleaner power source (for example, from a 12 v supply). it is also recommended to use a single ground plane for the entire board. experience has repeatedly shown that the noise performance is the same or better with a single ground plane. using multiple ground planes can be detrimental because each separate ground plane is smaller, and long ground loops can result. in some cases, using separate ground planes is unavoidable. for those cases, it is recommended to at least place a single ground plane under the ad9887. the location of the split should be at the receiver of the digital outputs. for this case it is even more important to place components wisely because the current loops will be much longer (current takes the path of least resistance). an example of a current loop: p o w e r p l a n e a d 9 8 8 7 d i g i t a l o u t p u t t r a c e a n a l o g g r o u n d p l a n e d i g i t a l g r o u n d p l a n e d i g i t a l d a t a r e c e i v e r figure 39. example of a current loop pll place the pll loop ?lter components as close to the filt pin as possible. do not place any digital or other high-frequency traces near these components. use the values suggested in the data sheet with 10% tolerances or less. outputs (both data and clocks) try to minimize the trace length that the digital outputs have to drive. longer traces have higher capacitance, which require more current that causes more internal digital noise. shorter traces reduce the possibility of reflections. adding a series resistor of value 50 ? C200 ? can suppress reflec- tions, reduce emi, and reduce the current spikes inside of the ad9887. if series resistors are used, place them as close to the ad9887 pins as possible (try not to add vias or extra length to the output trace in order to get the resistors closer). if possible, limit the capacitance that each of the digital outputs drives to less than 10 pf. this can easily be accomplished by keeping traces short and by connecting the outputs to only one device. loading the outputs with excessive capacitance will increase the current transients inside of the ad9887 creating more digital noise on its power supplies. digital inputs the digital inputs on the ad9887 were designed to work with 3.3 v signals. any noise that gets onto the hsync input trace will add jitter to the system. therefore, minimize the trace length and do not run any digital or other high-frequency traces near it. voltage reference bypass with a 0.1 f capacitor. place as close to the ad9887 pin as possible. make the ground connection as short as possible. refout is easily connected to refin with a short trace. avoid making this trace any longer than it needs to be. when using an external reference, the refout output, while unused, still needs to be bypassed with a 0.1 f capacitor in order to avoid ringing.
rev. 0 C40C c01026C0-10/01(0) printed in u.s.a. ad9887 160-lead mqfp (s-160) 1.238 (31.45) 1.228 (31.20) sq 1.219 (30.95) 0.026 (0.65) bsc * lead pitch 1.106 (28.10) 1.102 (28.00) sq 1.098 (27.90) 0.998 (25.35) bsc sq 0.015 (0.38) 0.012 (0.30) lead width 0.009 (0.22) 121 160 1 120 40 80 81 top view (pins down) pin 1 41 0.160 (4.07) max 0.041 (1.03) 0.035 (0.88) 0.029 (0.73) 0.010 (0.25) min 0.145 (3.67) 0.135 (3.42) 0.125 (3.17) seating plane 0.004 (0.10) max * the actual position of each lead is within 0.0047 (0.12) from its ideal position when measured in the lateral direction. center figures are typical unless otherwise noted. controlling dimensions are in millimeters. inch dimensions are rounded-off millimeter equivalents for reference only and are not appropriate for use in design. outline dimensions dimensions shown in inches and (mm).

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